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Scoreboarding is a centralized method, first used in the CDC 6600 computer, for dynamically scheduling a pipeline so that the instructions can execute out of order when there are no conflicts and the hardware is available.[1]

In a scoreboard, the data dependencies of every instruction are logged. Instructions are released only when the scoreboard determines that there are no conflicts with previously issued and incomplete instructions. If an instruction is stalled because it is unsafe to continue, the scoreboard monitors the flow of executing instructions until all dependencies have been resolved before the stalled instruction is issued.

Scoreboarding is essentially a hardware implementation of the same underlying algorithm seen in dataflow languages, where the same logic is applied in the programming language runtime.


Instructions are decoded in order and go through the following four stages.

  1. Issue: The system checks which registers will be read and written by this instruction. This information is remembered as it will be needed in the following stages. In order to avoid output dependencies (WAW – Write after Write) the instruction is stalled until instructions intending to write to the same register are completed. The instruction is also stalled when required functional units are currently busy.
  2. Read operands: After an instruction has been issued and correctly allocated to the required hardware module, the instruction waits until all operands become available. This procedure resolves read dependencies (RAW – Read after Write) because registers which are intended to be written by another instruction are not considered available until they are actually written.
  3. Execution: When all operands have been fetched, the functional unit starts its execution. After the result is ready, the scoreboard is notified.
  4. Write Result: In this stage the result is about to be written to its destination register. However, this operation is delayed until earlier instructions—which intend to read registers this instruction wants to write to—have completed their read operands stage. This way, so called data dependencies (WAR – Write after Read) can be addressed.

Data structure[edit]

To control the execution of the instructions, the scoreboard maintains three status tables:

  • Instruction Status: Indicates, for each instruction being executed, which of the four stages it is in.
  • Functional Unit Status: Indicates the state of each functional unit. Each function unit maintains 9 fields in the table:
    • Busy: Indicates whether the unit is being used or not
    • Op: Operation to perform in the unit (e.g. MUL, DIV or MOD)
    • Fi: Destination register
    • Fj,Fk: Source-register numbers
    • Qj,Qk: Functional units that will produce the source registers Fj, Fk
    • Rj,Rk: Flags that indicates when Fj, Fk are ready for and are not yet read.
  • Register Status: Indicates, for each register, which function unit will write results into it.

The algorithm[edit]

The detailed algorithm for the scoreboard control is described below:

 function issue(op, dst, src1, src2)
    wait until (!Busy[FU] AND !Result[dst]); // FU can be any functional unit that can execute operation op
    Busy[FU] ← Yes;
    Op[FU] ← op;
    Fi[FU] ← dst;
    Fj[FU] ← src1;
    Fk[FU] ← src2;
    Qj[FU] ← Result[src1];
    Qk[FU] ← Result[src2];
    Rj[FU] ← Qj[FU] == 0;
    Rk[FU] ← Qk[FU] == 0;
    Result[dst] ← FU;
 function read_operands(FU)
    wait until (Rj[FU] AND Rk[FU]);
    Rj[FU] ← No;
    Rk[FU] ← No;
 function execute(FU)
    // Execute whatever FU must do
 function write_back(FU)
    wait until (∀f {(Fj[f]≠Fi[FU] OR Rj[f]=No) AND (Fk[f]≠Fi[FU] OR Rk[f]=No)})
    foreach f do
        if Qj[f]=FU then Rj[f] ← Yes;
        if Qk[f]=FU then Rk[f] ← Yes;
    Result[Fi[FU]] ← 0; // 0 means no FU generates the register's result
    RegFile[Fi[FU]] ← computed value;
    Busy[FU] ← No;


The scoreboarding method must stall the issue stage when there is no functional unit available. In this case, future instructions that could potentially be executed will wait until the structural hazard is resolved. Some other techniques like Tomasulo algorithm can avoid the structural hazard and also resolve WAR and WAW dependencies with Register renaming.

See also[edit]


  1. ^ Thornton, James E. (1965). "Parallel operation in the control data 6600". Proceedings of the October 27–29, 1964, fall joint computer conference, part II: very high speed computer systems. AFIPS '64. San Francisco, California: ACM. pp. 33–40. doi:10.1145/1464039.1464045.
  • Glenford Myers, "Register scoreboarding on a microprocessor chip", United States Patent 4891753

External links[edit]