This article relies largely or entirely on a single source. (February 2021)
Semulation in computer science
Digital hardware is described using hardware description languages (HDL) like VHDL, Verilog or System Verilog. These descriptions are simulated together with a problem-specific testbench. The initial functional verification of most IP designs is done via simulation at register transfer level (RTL) or gate level. In an event driven simulation method the code must be processed sequential by a CPU, because a normal computer is not able to process the implemented hardware parallel. This sequential approach leads to long simulation times especially in complex systems on chip (SoC) designs.
After simulation the RTL description must be synthesized to fit in the final hardware (e.g. FPGA, ASIC). This step brings a lot of uncertainties because the real hardware is normally not as ideal as the simulation model. The differences between real world and simulation are a major reason why emulation is used in hardware design.
Generally the simulation and emulation environment are two independent systems. Semulation is a symbiosis of both methods. In semulation one part of a hardware design is processed sequential in software (e.g. the testbench) while the other part is emulated.
An example design flow for semulation is depicted in the following block chart:
The database holds the design and testbench files and the information about the block whether it will be simulated or emulated. The left part shows the normal simulation path where the design files must be compiled for an HDL simulator. The right part of the state chart handles the flow for the emulation system. Design files for the FPGA must be synthesized to the appropriate target technology. A major point in semulation is the connection between the emulation system and the HDL simulator. The interface is necessary for the simulator to handle the connected hardware.
Advantages of Semulation
- Simulation acceleration: Simulating huge designs with an HDL simulator is a tedious task. When the designer transfers parts of the design to an emulation system and co-simulates them with the HDL simulation, the simulation run times can be decreased.
- Using real hardware early in the design flow.
- D. Scheurer and S. Reichör, SEmulation: Turbocharging the FPGA Development Process. White Paper, Altera Corporation