Talk:Quadruple data rate

Why would someone use quadruple data rate rather than doubling the clock speed of a DDR bus? At what time do transfers happen? Does everything on the bus need to have it's own frequency multiplier? Does anyone other than Intel use it? Aij 00:52, 29 May 2006 (UTC)[reply]

Now Intel has their Xeons with 1333MHz FSBs. Is that a quad-pumped 333MHz FSB or what? It might be good to include that in the article. Geekosaurus 26 June 2006

Increasing the clock speed can be a very difficult thing to do in terms of 1) getting stable and cheap oscillators, 2) signal crosstalk, 3) capacitance/inductance of the lines causing clock skew, etc . . . but could someone with a good knowledge of "quad pumping" give a slightly more in-depth view of how this is accomplished? Are there simply 4x as many 32-bit outputs being bussed along? That seems slightly specious. 128.173.52.12

From asking people around here, the only explanation I've been able to get for why you would clock the data faster than the clock is that the data lines generally go more directly from point A to point B, whereas the clock signal needs to go to basically every point on the chip, and can't be clocked as high due to all the additional capacitance n'at. So apparently it's not just making the bus wider. (But this is all just hear say.) Aij 21:50, 19 October 2006 (UTC)[reply]

I haven't the faintest idea, really, but I would assume it relies on the fact that there is a rise and fall time, and hence transmits on the leading and trailing edge of both polarities of the signal, or that it transmits on zero crossing and the high/low polarity. Zuiram 80.202.245.178 16:45, 9 December 2006 (UTC)[reply]

According to Quad Data Rate SDRAM, the quadruple data rate is acheived in RAM by being able to read and write to the module at the same time, but that doesn't fit in with this version of QDR. I'm as lost as the rest of you. I can see how a digital signal could transfer 4 bits per clock cycle, but I'm no expert on electronics though. KennethJ 01:01, 27 December 2006 (UTC)[reply]

AGP has a strobe signal, so the clock is not used in reading the data from the bus. The strobe simply clocks 4x faster than the clock signal. --86.144.237.86 18:34, 29 December 2006 (UTC)[reply]

This page duplicates http://en.wikipedia.org/wiki/Quad_Data_Rate_SRAM where many answers to the above can be found.