Talk:Wishbone (computer bus)

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Rather than saying that a WB is a "hardware computer bus" I would say that it is a "bus interface" since the standard doesn't prescribe any bus, i.e. the same given WB interface can be connected to many different kind of buses. — Preceding unsigned comment added by 140.105.17.191 (talk) 08:18, 21 August 2015 (UTC)[reply]

Don't mean to be too picky, but the graphics on this page are kind of crude, and would probably best not be in JPEG format... AnonMoos (talk) 17:44, 8 July 2008 (UTC)[reply]

It seems to me, most of the graphics is printsreened from the Wishbone specification PDF. --Volodymyr Obrizan (talk) 07:46, 8 January 2010 (UTC)[reply]

Comparison to the Avalon Bus

It is slightly weird that the description of Wishbone is based on a comparison with the Altera Avalon bus (interconnect fabric), especially since Wikipedia doesn't contain an entry about Avalon. —Preceding unsigned comment added by 77.110.39.122 (talk) 15:04, 18 November 2008 (UTC)[reply]

impossibility of this mapping between Wishbone and Avalon

I don't know what is Avalon. But because of formulas written on this article, only cyc and we can not be used to recombine to write_n and read_n. Given two compound propositions composed of proposition variables p and q and different from p and q, if you want to get p and q back from only that two compound propositions, then that two compound propositions must be that one is "p xor q" or "p ↔ q" and another one is p, q, ~p or ~q.

Sorry for my poor English.--LungZeno (talk) 05:06, 4 July 2012 (UTC)[reply]