The Motorola 68020 ("sixty-eight-oh-twenty", "sixty-eight-oh-two-oh" or "six-eight-oh-two-oh") is a 32-bit microprocessor from Motorola, released in 1984. It is the successor to the Motorola 68010 and is succeeded by the Motorola 68030. A lower cost version was also made available, known as the 68EC020. In keeping with naming practices common to Motorola designs, the 68020 is usually referred to as the '020, pronounced oh-two-oh or oh-twenty".
The 68020 had 32-bit internal and external data and address buses, compared to the early models with 16-bit data and 24-bit address buses. Newer packaging methods allowed the '020 to feature more external pins without the large size that the earlier dual in-line package method required. The 68EC020 lowered cost through a 24-bit address bus. The 68020 was produced at speeds ranging from 12 MHz to 33 MHz.
Improvements over 68010
The 68020 added many improvements to the 68010 including a 32-bit arithmetic logic unit (ALU), external data bus and address bus, and new instructions and addressing modes. The 68020 (and 68030) had a proper three-stage pipeline. Though 68010 had a "loop mode", which sped loops through what was effectively a tiny instruction cache, it had only two memory location and was thus little used. The 68020 replaced this with a proper instruction cache of 256 bytes, the first 68k series processor to feature true onboard cache memory.
The previous 68000 and 68010 processors could only access word (16 bit) and longword (32 bit) data if it were word-aligned (located at an address that is evenly divisible by 2). The 68020 had no alignment restrictions on data access. However, unaligned longword accesses were often much slower than aligned accesses.
The 68020 has a coprocessor interface supporting up to eight coprocessors. The main CPU recognizes "F-line" instructions (with the four most significant opcode bits all one), and uses special bus cycles to interact with a coprocessor to execute these instructions. Two types of coprocessors were defined, the floating point unit (MC68881 or MC68882 FPU) and the paged memory management unit (MC68851 PMMU). Only one PMMU can be used with a CPU. In principle multiple FPUs could be used with a CPU, but it was not commonly done. The coprocessor interface is asynchronous, so it is possible to run the coprocessors at a different clock rate than the CPU.
Multiprocessing support was implemented externally by the use of a RMC pin to indicate an indivisible read-modify-write cycle in progress. All other processors had to hold off memory accesses until the cycle was complete. Software support for multiprocessing included the TAS, CAS and CAS2 instructions.
In a multiprocessor system, coprocessors could not be shared between CPUs. To avoid problems with returns from coprocessor, bus error, and address error exceptions, it was generally necessary in a multiprocessor system for all CPUs to be the same model, and for all FPUs to be the same model as well.
The new instructions included some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system (which were removed in the 68060), some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger multiply (32×32→64 bits) and divide (64÷32→32 bits quotient and 32 bits remainder) instructions, and bit field manipulations.
While the 68000 had 'supervisor mode', it did not meet the Popek and Goldberg virtualization requirements due to the single instruction 'MOVE from SR' being unprivileged but sensitive. Under the 68010 and later, this was made privileged, to better support virtualization software.
The new addressing modes added scaled indexing and another level of indirection to many of the pre-existing modes, and added quite a bit of flexibility to various indexing modes and operations. Though it was not intended, these new modes made the 68020 very suitable for page printing; most laser printers in the early '90s had a 68EC020 at their core.
The 68020 had a minimal 256 byte direct-mapped instruction cache, arranged as 64 four-byte entries. Although small, it still made a significant difference in the performance of many applications. The resulting decrease in bus traffic was particularly important in systems relying heavily on DMA.
The 68020 was used in the Apple Macintosh II and Macintosh LC personal computers, as well as Sun 3 workstations, the Hewlett-Packard 8711 Series Network Analyzers and later members of the HP 9000/300 family and the Alpha Microsystems AM-2000. Also the 68020 was an alternative upgrade to the Sinclair QL computer's 68008 in the Super Gold Card interface by Miracle Systems.
The Amiga 2500 and A2500UX was shipped with the A2620 Accelerator using a 68020, a 68881 floating point unit and the 68851 Memory Management Unit. The 2500UX shipped with Amiga Unix, requiring an '020 or '030 processor.
It is also the processor used on board TGV trains to decode signalling information which is sent to the trains through the rails. It is further being used in the flight control and radar systems of the Eurofighter Typhoon combat aircraft.
For more information on the instructions and architecture see Motorola 68000.
The 68EC020 is a microprocessor from Motorola. It is a lower cost version of the Motorola 68020. The main difference between the two is that the 68EC020 only has a 24-bit address bus, rather than the 32-bit address bus of the full 68020, and thus is only able to address 16 MB of memory.
The Commodore Amiga 1200 computer and the Amiga CD32 games console used the cost-reduced 68EC020; the Namco System 22 arcade board has also used this processor. It also found use in laser printers. Apple used it in the LaserWriter IIɴᴛx. Kodak used it in the Ektaplus 7016PS, and Dataproducts used it in the LZR 1260.
|Work frequency||12.5 , 16.67 , 20 , 25 , 33 MHz (minimum 8 MHz, no on-chip clock generation)|
|Voltage supply||5 V|
|Maximum power||1.75 W|
|Production process||HCMOS, 3/8" silicon piece|
|Chip carrier||PGA 169 (114 pins used) 34.16 x 34.16 mm(53 °C/W without heatsink)|
|Address bus||32-bit (4 GB directly linear accessible)|
|Instruction set||101 CISC instructions|
|Cache||256 byte ICache|
|Handling Branches||Branch Prediction:
|Performance||5.36 MIPS @ 33MHz|
|This article needs additional citations for verification. (November 2007)|
- "MC68020 Signal Description, Appendix A, page 84". Retrieved 2010-01-17.
- "5.3.3 Read-Modify-Write Cycle". MC68020/MC68EC020 Microprocessors User's Manual UM Rev. 1.0. Freescale Semiconductor. 1995.
- Rafiquzzaman, M. (2005). Fundamentals of Digital Logic and Microcomputer Design. John Wiley & Sons. pp. 577–578. ISBN 978-0471733492.
- freescale.com - M68020UM/AD REV.2 Users manual
- Dandamudi, S. P. (2004). Guide to RISC Processors. p. 29. ISBN 0-387-21017-2.
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