Memory timings or RAM timings measure the performance of DRAM memory using four parameters: CL, tRCD, tRP, and tRAS in units of clock cycles; they are commonly written as four numbers separated with dashes, e.g. 7-8-8-24. The fourth (tRAS) is often omitted, and a fifth, the Command rate, sometimes added (normally 2T or 1T - also 2N, 1N). These parameters specify the latencies (time delays) that affect speed of random access memory. Lower numbers imply faster performance.
Modern DIMMs include a Serial Presence Detect (SPD) ROM chip that contains recommended memory timings for automatic configuration. The BIOS on a PC may allow the user to make adjustments in an effort to increase performance (with possible risk of decreased stability) or, in some cases, to increase stability (by using suggested timings).
Note: Memory bandwidth measures the throughput of memory, and is closely related to memory timings. It is possible for advances in bandwidth technology to have an undesirable impact on latency. For example, DDR memory has been superseded by DDR2, and yet DDR2 has significantly higher latency at the same clock frequencies. However, DDR2 can be clocked faster, decreasing its cycle time. Now DDR2 has been superseded by DDR3, and the trend of a higher latency coupled with a higher clock speed has continued.
Increasing memory bandwidth, even while increasing memory latency, can improve the performance of a computer system with multiple processors, and also systems with processors that have multiple execution threads.
|CAS latency||CL||The time between sending a column address to the memory and the beginning of the data in response. This is the time it takes to read the first bit of memory from a DRAM with the correct row already open.|
|Row Address to Column Address Delay||TRCD||The number of clock cycles required between the opening of a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL.|
|Row Precharge Time||TRP||The number of clock cycles required between the issuing of the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.|
|Row Active Time||TRAS||The number of clock cycles required between a bank active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlapping with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + (2 * CL).|
Handling in BIOS
- Posted by Alex Watson, possibly repost from original content on custompc.com [unclear]. "The life and times of the modern motherboard". 2007-11-27. Retrieved 2 February 2013.