Talk:Logic synthesis

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Levels of logic[edit]

most dad referring to the logic depth which means the number of gates from the inputs to the outputs. I agree it seems a bit confusing. Philhower (talk) 18:55, 14 October 2008 (UTC)

Behavioral synthesis[edit]

There is some false information about behavioral synthesis and high level synthesis here. These are NOT the same. Also, the terms behavioral and high level refer to the *abstraction level* not to the *language* used to write the model, which is totally different. For instance it is possible to write both TLM and RTL models using SystemC, TLM ones are NOT synthesizable. —Preceding unsigned comment added by 81.220.160.209 (talk) 21:42, 3 February 2009 (UTC)

Xilinx ISE synthesis software proposed for deletion![edit]

Some deletists want to remove the Xilinx ISE article. Please see the discussion at Wikipedia:Articles_for_deletion/Xilinx_ISE. Electron9 (talk) 01:35, 30 August 2010 (UTC)

Merge logic design here[edit]

I don't see difference, if the VLSI design cycle def is used there. I can see that in general it may refer to other stages, but it's all very fuzzy. Tijfo098 (talk) 20:29, 9 April 2011 (UTC)