VHDL

VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits.

History

VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.

The idea of being able to simulate these "documents" was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest cost, highest power efficiency, highest speed, or other requirements.

VHDL has a syntax that is essentially a subset of the Ada programming language, along with an added set of constructs to handle the parallelism inherent in hardware designs. VHDL is strongly-typed and case insensitive.

The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_logic and its vector version std_logic_vector.

The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE Std. 1076.2 added better handling of real and complex data types. IEEE Std. 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE Std. 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL; VITAL (VHDL Initiative Towards ASIC Libraries), and microwave circuit design extensions are worth mentioning here.

In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

Discussion

VHDL is a fairly general-purpose language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. This is similar to the capabilities of the Verilog language. VHDL is a strongly typed language, and as a result is considered by some to be superior to Verilog. In fact there has always been quite an intense debate which amounts to a holy war amongst developers over which is the superior language. However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall in both languages is the accidental production of transparent latches rather than D-type flip-flops as storage elements.

The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time). This is unlike many of the other computing languages such as BASIC, Pascal, C, or lower-level assembly language which runs at machine code level, which all run sequentially, one instruction at a time on von Neumann architectures.

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is actual hardware that is being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

Getting started with VHDL

The best way of learning VHDL is by 'doing it'. To start coding in VHDL, one would at the very least need a simulation tool. While very few open source VHDL simulators exists today, most commercial vendors offer free (but often limited) versions of their software.

Furthermore, it is highly recommended to use a synthesis tool even when you do not plan to test your code on real hardware. The reason for this is that you can often see the graphical representation (i.e. gates) of your code after synthesis. Seeing what kind of hardware correspond to your code is a very important step in learning any HDL and becoming a good designer.

As a side note, the graphical representation is sometimes available in two version: RTL (which is more generic) and technology-mapped gates (which is the RTL mapped to the cells that are available in the target hardware).

Today, almost all FPGA vendors offer free (but often limited) version of their complete toolchain. These tools are more than enough for the beginners to start with, and also sometimes include very valuable documents and tutorials for the beginners.

Vendor	Tool	License	Simulator	Synthesizer	RTL view	Gate view
Actel	Libero gold	one year free license	ModelSim Actel Edition	Synplify Actel Edition	no	yes
Altera	Quartus II	one year free license	none	Quartus II	yes	yes
Lattice	ispLever starter	one year free license	none	Synplify Lattice Edition	?	?
Xilinx	ISE webpack	free license	ModelSim Xilinx Edition	XST	yes	yes

Code examples

In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architecture and configurations. For example, an AND gate would look something like this:

-- (this is a VHDL comment)

-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;

-- this is the entity
entity my_and is
port ( IN1, IN2 : in std_logic; OUT1: out std_logic);
end entity;

-- here comes the architecture
architecture example of my_and is
begin
  OUT1 <= IN1 and IN2;
end example;

While the example above may seem very verbose to HDL beginners, one should keep in mind that many parts are optional. In addition, use of things such as std_logic type might at first seem an overkill. One could easily use the built-in 'bit' type and avoid the library import in the beginning. However, the 9-valued logic offers a very powerful simulation and debugging tool to the designer which currently does not exists in any other HDLs.

In the examples that follows, you will see that VHDL code can be written in a very compact form. However, the experienced designers usually avoid these compact form and use more verbose forms for the sake of readability and maintainability.

Synthesizeable constructs and VHDL templates

Originally, what would correspond to compilers in the HDL world, used a set of templates to identify the common hardware constructs in the HDL code (recall the VHDL is a hardware 'description' language, not a programming language). These templates can still be used today, although the HDL tools are much more sophisticated these days. The templates are usually what a 'old-school' digital hardware designer would use most when entering the HDL world. But they are also useful for those who are completely new to digital design.

Some digital components have multiple templates, consider for example a multiplexor with input A and B, selector S and output X:

MUX templates

 
-- template 1:
X <= A when S = '1' else B;

-- template 2:
with S select X <= A when '1' else B;

-- template 3:
process(A,B,S)
begin
  case S is
    when '1' => X <= A;
    when others => X <= B;
  end case;
end process;

-- template 4:
process(A,B,S)
begin
  if S = '1' then
    X <= A;
  else
    X <= B;
  end if;
end process;

The two last templates make use of what VHDL calls 'sequential' code. The sequential sections are always placed inside a process and have a slightly different syntax which may resemble of more traditional programming languages.

Latch templates

A transparent latch is basically one bit of memory which is updatded when an enable signal is rasied:

-- latch template 1:
Q <= D when Enable = '1' else Q;

-- latch template 2:
process(D,Enable)
begin
  if Enable = '1' then
    Q <= D;
  end if;
end process;

A SR-latch uses a set and reset signal instead:

-- SR-latch template 1:
Q <= '1' when S = '1' else
  '0' when R = '1' else
  Q;


-- SR-latch template 2:
process(S,R)
begin
  if S = '1' then
    Q <= '1';
  elsif R = '1' then
    Q <= '0';
  end if;
end process;


-- This one is an RS-latch (i.e. reset dominates)
process(S,R)
begin
  if R = '1' then
    Q <= '0';
  elsif S = '1' then
    Q <= '1';
  end if;
end process;

D-type flip-flops

The D-type flip-flops sample an incoming signal at the rising or falling edge of a clock.

-- simplest DFF template (not recommended)
Q <= D when rising_edge(CLK);

-- recommended DFF template:
process(CLK)
begin
  -- use falling_edge(CLK) to sample at the falling edge instead
  if rising_edge(CLK) then
    Q <= D;
  end if;
end process;
  
-- alternative DFF template:
process
begin
  wait until rising_edge(CLK);
  Q <= D;  
end process;

Some flip-flops also have Enable signals and asynchronous or synchronous Set and Reset signals:

-- template for asynchronous reset with clock enable:
process(CLK, RESET)
begin
  if RESET = '1' then   -- or '0' if RESET is active low...
    Q <= '0';
  elsif rising_edge(CLK) then
    if Enable = '1' then  -- or '0' if Enable is active low...
      Q <= D;
    end if;
  end if;
end process;

-- template for synchronous reset with clock enable:
process(CLK)
begin
  if rising_edge(CLK) then
    if RESET = '1' then 
      Q <= '1';
    elsif Enable = '1' then  -- or '0' if Enable is active low...
      Q <= D;
    end if;
  end if;
end process;

A common beginner mistake is to have a set or reset input but not use it. For example, consider thet second template below. It is neither equal to the first (DFF-SR) or the last (DFF-R) template.

-- D-type flip-flop with asynchronous set and reset (set dominates)
process(CLK, RESET, SET)
begin
  if SET = '1 then  Q <= '1';    
  elsif RESET = '1' then   Q <= '0';
  elsif rising_edge(CLK) then  Q <= D;  
  end if;
end process;

-- BAD VHDL: this does NOT make the flip-flop a DFF with reset!!
-- this incorrect template will generate a flip-flop plus a transparent latch!!
process(CLK, RESET, SET)
begin
  if SET = '1 then  
  	-- do nothing. Q is not set here...
  elsif RESET = '1' then   Q <= '0';
  elsif rising_edge(CLK) then  Q <= D;  
  end if;
end process;

-- the correct template for the DFF-R above would be:
process(CLK, RESET)
begin
  if RESET = '1' then   Q <= '0';
  elsif rising_edge(CLK) then  Q <= D;  
  end if;
end process;

Three-state logic

The std_logic type supports three-state logic. If the target device does not have native three-state cells, the synthesizer tool will (usually) automatically use multiplexors to achieve the same functionality.

-- Q must be defined as "inout" in the entity.

-- write to the 3-state port if enabled
Q <= D when Enable = '1' else 'Z';

-- read from it and use it as it was a normal input:
some_signal <= Q and some_other_signal;

Counter example

The following example is a counter with asynchronous RESET, parallel load and configurable width. It demonstrares the use of the unsigned type and VHDL generics

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;    -- for the unsigned type,

entity counter_example is
generic ( WIDTH : integer := 32);
port (
  CLK : in std_logic;
  RESET : in std_logic;

  DATA : in unsigned(WIDTH-1 downto 0);  
  LOAD : in std_logic;
  
  Q : out unsigned(WIDTH-1 downto 0));
end entity;

architecture behav of counter_example is
signal cnt : unsigned(WIDTH-1 downto 0);
begin
  -- write output
  Q <= cnt;

  -- the counter:
  process(RESET, CLK)
  begin
    if RESET = '1' then
      cnt <= (others => '0');
    elsif rising_edge(CLK) then
      if LOAD = '1' then
        cnt <= DATA;
      else
        cnt <= cnt + 1;
      end if;
    end if;
  end process;
end behav;

Fibonacci series

The following example is slightly more complex:

--  Fib.vhd
--
--  Fibonacci number sequence generator

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Fibonacci is
port
(
    Reset       : in    std_logic;
    Clock       : in    std_logic;
    Number      : out   unsigned(31 downto 0)
);
end Fibonacci;

architecture Rcingham of Fibonacci is

    signal  Previous    : natural;
    signal  Current     : natural;
    signal  Next_Fib    : natural;

begin

    Adder:
    Next_Fib <= Current + Previous;

    Registers:
    process (Clock, Reset) is
    begin
        if Reset = '1' then
            Previous <= 1;
            Current  <= 1;
        elsif rising_edge(Clock) then
            Previous <= Current;
            Current  <= Next_Fib;
        end if;
    end process Registers;

    Number <= to_unsigned(Previous, 32);

end Rcingham;

When simulated, it generates the Fibonacci sequence successfully, until Next_Fib overflows the range of the natural type.

When synthesized with an FPGA vendor's tools, an "Adder" module was implemented, as hoped for. Otherwise, the assignment statement would have to be replaced by a component instantiation to logic that implements that function.

Simulation-only constructs

A large subset of VHDL can not be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL and is used for prototyping, simulation and debugging only.

For example, the following code will generate a clock with the frequency of 50 MHz. It can for example be used to drive a clock input in a design during simulation. It is however a simulation only constructs and can not be implemented in hardware.

process
begin
  CLK <= '1'; wait for 10 ns;
  CLK <= '0'; wait for 10 ns;
end process;

The simulation only constructs can be used to build complex waveforms in very short time. Such waveform can be used, for example, as test vectors for a complex design.

process
begin
  wait until START = '1'; -- wait until START is high
  
  for i in 1 to 10 loop -- then wait for a clock periods...
    wait until rising_edge(CLK);
  end loop;

  for i in 1 to 10 loop 	-- write numbers 1 to 10 to DATA, 1 every cycle
    DATA <= to_unsigned(i, 8);
    wait until rising_edge(CLK);
  end loop;

  -- wait until the output changes
  wait until RESULT'event;
  
  -- now raise ACK for clock period
  ACK <= '1';
  wait until rising_edge(CLK);
  ACK <= '0';
  

  -- and so on...
end process;

Further reading

• Johan Sandstrom (October 1995). "Comparing Verilog to VHDL Syntactically and Semantically". Integrated System Design. EE Times. — Sandstrom presents a table relating VHDL constructs to Verilog constructs.

See also

• Verilog
• SystemC
• Register transfer level
• Electronic design automation

External links

Tutorials, FAQs and guides

• The FAQ of news://comp.lang.vhdl
• Designers Guide to VHDL
• IEEE standard 1164
• A VHDL quick reference card

Interested bodies

• IEEE VASG (VHDL Analysis and Standardization Group) - Official VHDL Working Group
  • VHDL-200x - Source packages and test suites for next generation of VHDL (able to be used with current VHDL-93 tools)
• OpenCores OpenSource cores (logic designs)

Examples

• '99 bottles of beer' in VHDL to compare with other programming languages
• A VHDL reference design - UART (Testbench for the design)
• PN Sequence Generator VHDL example see: (PN Sequences)

Software

• GHDL, a complete Free Software VHDL compiler/simulator, built on top of GCC.
• ASIMUT, a free/open-source VHDL simulator, included in ALLIANCE. ALLIANCE is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.
• VHDL Mode, an Emacs major mode for editing VHDL code

Hardware

• Xilinx manufacturer of programmable logic devices [1]
• Altera Corporation with FPGA, CPLD, and structured ASIC [2]