Iron law of processor performance: Difference between revisions
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<math display="block">\frac{Instructions}{Program} \times \frac{Clock Cycles}{Instruction} \times \frac{Time}{Clock Cycles}</math>The [[instruction set architecture]] impacts <math>\tfrac{Instructions}{Program} \times \tfrac{Clock Cycles}{Instruction} </math> as <math>\tfrac{Time}{Clock Cycles}</math> is largely determined by the manufacturing technology. Classic [[Complex instruction set computer|Complex Instruction Set Computer]] (CISC) ISAs optimized <math>\tfrac{Instructions}{Program}</math> by providing a larger set of more complex [[Machine code|CPU instructions]]. Generally speaking, however, complex instructions inflate the number clock cycles per instruction (<math>\tfrac{ClockCycles}{Instruction}</math>) because they must be decoded into simpler ''micro-operations'' correlating to the actual operations performed by the hardware. After converting X86 binary to the micro-operations used internally, the total number of operations is very close to what is produced for a comparable RISC ISA<ref name=":0">{{cite arxiv|eprint=1607.02318|class=cs.AR|first1=Christopher|last1=Celio|first2=Palmer|last2=Dabbelt|title=The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V|date=2016-07-08|last3=Patterson|first3=David A.|last4=Asanović|first4=Krste}}</ref>. |
<math display="block">\frac{Instructions}{Program} \times \frac{Clock Cycles}{Instruction} \times \frac{Time}{Clock Cycles}</math>The [[instruction set architecture]] impacts <math>\tfrac{Instructions}{Program} \times \tfrac{Clock Cycles}{Instruction} </math> as <math>\tfrac{Time}{Clock Cycles}</math> is largely determined by the manufacturing technology. Classic [[Complex instruction set computer|Complex Instruction Set Computer]] (CISC) ISAs optimized <math>\tfrac{Instructions}{Program}</math> by providing a larger set of more complex [[Machine code|CPU instructions]]. Generally speaking, however, complex instructions inflate the number clock cycles per instruction (<math>\tfrac{ClockCycles}{Instruction}</math>) because they must be decoded into simpler ''micro-operations'' correlating to the actual operations performed by the hardware. After converting X86 binary to the micro-operations used internally, the total number of operations is very close to what is produced for a comparable RISC ISA<ref name=":0">{{cite arxiv|eprint=1607.02318|class=cs.AR|first1=Christopher|last1=Celio|first2=Palmer|last2=Dabbelt|title=The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V|date=2016-07-08|last3=Patterson|first3=David A.|last4=Asanović|first4=Krste}}</ref>. |
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The iron law of processor performance makes this trade-off explicit and pushes for optimization of <math>\tfrac{Time}{Program}</math>as a whole, not just a single sub-component. While the iron law is credited for sparking the development of RISC architectures{{Citation needed|date=September 2021}}, it does not imply that a simpler ISA is '''always''' faster. If that was the case, |
The iron law of processor performance makes this trade-off explicit and pushes for optimization of <math>\tfrac{Time}{Program}</math>as a whole, not just a single sub-component. While the iron law is credited for sparking the development of RISC architectures{{Citation needed|date=September 2021}}, it does not imply that a simpler ISA is '''always''' faster. If that was the case, the fastest ISA would consist of simple binary logic{{Citation needed|date=September 2021}}. A single CISC instruction ''can'' be faster when it enables multiple consecutive micro-operations to be performed one clock cycle. However, a well designed architecture can achieve the same performance gains without bloating the core ISA via modular extensions, [[compressed instruction set|compressed instructions]], and macro-operation fusion<ref>{{Cite web|last=Engheim|first=Erik|date=2020-12-28|title=The Genius of RISC-V Microprocessors|url=https://erik-engheim.medium.com/the-genius-of-risc-v-microprocessors-b19d735abaa6|access-date=2021-03-11|website=Medium|language=en}}</ref><ref name=":0" /><ref>{{Citation|last=Celio|first=Christopher|title=A Comparison of RISC V, ARM, and x86|url=https://www.youtube.com/watch?v=Ii_pEXKKYUg|publication-date=2016-07-26|language=en|access-date=2021-03-11}}</ref>. |
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== See also == |
== See also == |
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Revision as of 03:03, 2 September 2021
In computer architecture, the iron law of processor performance is a mathematical formulation describing how the primitive instructions processors use to perform tasks relate to performance[1]. It was coined by Douglas Clark[2] based on research performed by Clark and Joel Emer in the 1980s[3]. This insight spurred the development RISC[citation needed] (Reduced Instruction Set Computers) whose instruction set architectures use a smaller set of primitive CPU instructions.
Explanation
The performance of a processor can be summarized as the time it takes to execute a program: . This can be further broken down into three factors:[4]
The instruction set architecture impacts as is largely determined by the manufacturing technology. Classic Complex Instruction Set Computer (CISC) ISAs optimized by providing a larger set of more complex CPU instructions. Generally speaking, however, complex instructions inflate the number clock cycles per instruction () because they must be decoded into simpler micro-operations correlating to the actual operations performed by the hardware. After converting X86 binary to the micro-operations used internally, the total number of operations is very close to what is produced for a comparable RISC ISA[5].
The iron law of processor performance makes this trade-off explicit and pushes for optimization of as a whole, not just a single sub-component. While the iron law is credited for sparking the development of RISC architectures[citation needed], it does not imply that a simpler ISA is always faster. If that was the case, the fastest ISA would consist of simple binary logic[citation needed]. A single CISC instruction can be faster when it enables multiple consecutive micro-operations to be performed one clock cycle. However, a well designed architecture can achieve the same performance gains without bloating the core ISA via modular extensions, compressed instructions, and macro-operation fusion[6][5][7].
See also
References
- ^ Eeckhout, Lieven (2010). Computer Architecture Performance Evaluation Methods. Morgan & Claypool. pp. 5–6. ISBN 9781608454679. Retrieved 9 March 2021.
- ^ Joel, Emer (2021-04-13), YArch 2021 Keynote, retrieved 2021-09-02
- ^ A Characterization of Processor Performance in the VAX-11/780, Joel S. Emer, Douglas W. Clark, 1984, IEEE
- ^ Asanovic, Krste (2019). "Lecture 4 - Pipelining" (PDF). Department of Electrical Engineering and Computer Sciences at UC Berkeley (Lecture Slides). p. 2. Archived from the original on 2020-03-11. Retrieved 2020-03-11.
- ^ a b Celio, Christopher; Dabbelt, Palmer; Patterson, David A.; Asanović, Krste (2016-07-08). "The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V". arXiv:1607.02318 [cs.AR].
- ^ Engheim, Erik (2020-12-28). "The Genius of RISC-V Microprocessors". Medium. Retrieved 2021-03-11.
- ^ Celio, Christopher (2016-07-26), A Comparison of RISC V, ARM, and x86, retrieved 2021-03-11
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