Gem5: Difference between revisions
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The '''gem5''' simulator is an [[Open source|open-source]] [[Computer architecture simulator|system-level and processor simulator]]. It is utilized in academic research and in industry by companies such as [[ARM (company)|ARM]] Research, [[Amd|AMD]] Research, [[Google]], [[Micron_Technology|Micron]], Metempsy, [[Hewlett-Packard|HP]], and [[Samsung]].<ref name=":0">{{cite web|url=http://www.gem5.org/about/|title=gem5: About|last=|first=|date=|website=|url-status=live|archive-url=|archive-date=|accessdate=14 November 2019}}</ref> |
The '''gem5''' simulator is an [[Open source|open-source]] [[Computer architecture simulator|system-level and processor simulator]]. It is utilized in academic research and in industry by companies such as [[ARM (company)|ARM]] Research, [[Amd|AMD]] Research, [[Google]], [[Micron_Technology|Micron]], Metempsy, [[Hewlett-Packard|HP]], and [[Samsung]].<ref name=":0">{{cite web|url=http://www.gem5.org/about/|title=gem5: About|last=|first=|date=|website=|url-status=live|archive-url=|archive-date=|accessdate=14 November 2019}}</ref> |
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Revision as of 19:43, 25 April 2022
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| Developer(s) | Community |
|---|---|
| Initial release | August 2011 |
| Stable release | v21.2.0.0
/ December 27, 2021 |
| Written in | C++, Python |
| Operating system | Linux |
| License | Revised BSD License |
| Website | www |
The gem5 simulator is an open-source system-level and processor simulator. It is utilized in academic research and in industry by companies such as ARM Research, AMD Research, Google, Micron, Metempsy, HP, and Samsung.[1]
History
gem5 was born out of the merger of m5 (CPU simulation framework) and GEMS (memory timing simulator).[2]
Features
gem5 is an event-driven simulator with multiple execution modes.[2]
- full-system emulation (simulating the whole OS) and syscall emulation (just user-space is emulated)
- multiple ISAs (Alpha, ARM, SPARC, MIPS, POWER, RISC-V, and x86 ISAs)[1]
- timing model for the full cache hierarchy with support for custom coherence protocols
- simplistic CPU, in-order CPU, out-of-order CPU
- serialize/deserialization from checkpoints
References
- ^ a b "gem5: About". Retrieved 14 November 2019.
{{cite web}}: CS1 maint: url-status (link) - ^ a b Binkert, Nathan; Sardashti, Somayeh; Sen, Rathijit; Sewell, Korey; Shoaib, Muhammad; Vaish, Nilay; Hill, Mark D.; Wood, David A.; Beckmann, Bradford; Black, Gabriel; Reinhardt, Steven K. (2011-08-31). "The gem5 simulator". ACM SIGARCH Computer Architecture News. 39 (2): 1. doi:10.1145/2024716.2024718.
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