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== References ==
== References ==
* [http://ai.eecs.umich.edu/~mirror/MIT78/MIT78.html The M.I.T. 1978 VLSI System Design Course]
* [http://ai.eecs.umich.edu/~mirror/MIT78/MIT78.html The M.I.T. 1978 VLSI System Design Course]
* [http://ic.hkstp.org/ip_mpw_about.html MPW service by Hong Kong Science Park]
* [http://lab.hkstp.org/e/default_home.asp?url=/e/customize/design_mpw.asp MPW service by Hong Kong Science Park]
* [http://www.mosis.com MOSIS]
* [http://www.mosis.com MOSIS]
* [http://cmp.imag.fr CMP Multi-Project Circuits]
* [http://cmp.imag.fr CMP Multi-Project Circuits]

Revision as of 03:37, 24 June 2009

Multi-Project Chip (MPC) or Multi-Project Wafer (MPW) services integrate onto microelectronics wafers a number of different integrated circuit designs from various teams including designs from private firms, students and researchers from universities. Because IC fabrication costs are extremely high, it makes sense to share mask and wafer resources to produce designs in low quantities. Worldwide, several MPW services are available from government-supported institutions or from private firms including MOSIS, CMP and Europractice.

The first well known MPW service was MOSIS (Metal Oxide Silicon Implementation Service), established by DARPA as a technical and human infrastructure for VLSI. MOSIS began in 1981 after Lynn Conway organized the first VLSI System Design Course at M.I.T. in 1978. MOSIS primarily services commercial users now but continues to serve university students and researchers.

With MOSIS, designs are submitted for fabrication using either open (i. e., non-proprietary) VLSI layout design rules or vendor proprietary rules. Designs are pooled into common lots and run through the fabrication process at foundries. The completed chips (packaged or unpackaged) are returned to customers.

Many silicon fabrication facilities offer MPW runs or a company can produce its own MPW, e.g. combine several of its own designs to form one wafer completely owned by the company. In the latter case, it may be profitable to use most of the wafer for production chips and a small portion for producing prototypes of next generation chips.

References