Jump to content

Talk:VHDL

Page contents not supported in other languages.
From Wikipedia, the free encyclopedia

This is an old revision of this page, as edited by Jiri Svoboda (talk | contribs) at 13:02, 21 February 2009 (→Removed weasel sentences: new section). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Please remove the Fibonacci example!

The Fibonacci example takes a lot of space and is of no real good. It is long, and boring, not very usefull VHDL and is almsot a copy of the counter example (which is also long and not very useful). It looks like someone was in love with the Fibonacci numbers and decided to add it to the VHDL page just because he could :(

If you guys really want to add something of value to the VHDL page, I suggest you add a picture of the generated hardware for each of the smaller examples. These can be obtained using, for example, the free version (Webpack) of Altera Quartus. I belive that showing the generated hardware would be of _MUCH_ more use to the people just browsing the VHDL pages trying to figure out what the heck it is... —Preceding unsigned comment added by 81.236.17.231 (talk) 09:24, 18 July 2008 (UTC)[reply]

I will remove the Fibonacci example in short if no one objects —Preceding unsigned comment added by 81.236.17.231 (talk) 19:30, 23 July 2008 (UTC)[reply]


Colorize Sample Source Code

Dose anybody know how to colorize source code samples in wiki? This job is well done by most text editors, but how to add it here?

  • You can use <source lang="VHDL"> ... </source>. I already updated the main page.

Colorized source code have 10x more readability, don't you agree? Neonil 11:12, 5 March 2007 (UTC)[reply]

P.S. Compare these two: Neonil 11:35, 5 March 2007 (UTC)[reply] 

-- (this is a VHDL comment)

-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;

-- this is the entity
entity name_of_entity is
   port ( 
         IN1 : in std_logic;
         IN2 : in std_logic;
         OUT1: out std_logic);
end entity name_of_entity;

-- here comes the architecture
architecture name_of_architecture of name_of_entity is

-- Internal signals and components would be defined here

begin

  OUT1 <= IN1 and IN2;

end architecture name_of_architecture;

I use trac to do it which calls enscript which dumps HTML. I will try to do the sample code right now. — RevRagnarok Talk Contrib 12:25, 5 March 2007 (UTC)[reply]
No luck - it uses CSS to do all the coloring, and I don't have time to play with it this morning. Maybe tonite if I get a chance. — RevRagnarok Talk Contrib 12:29, 5 March 2007 (UTC)[reply]

PPS. I found some sort of source code decoration in Object Pascal, but not sure how it works... Why I can't see no wiki tag for monospace font? Hmmm.... Neonil 16:50, 5 March 2007 (UTC)[reply]

Misleading statement about VHDL

In the Discussion section the sentence `However, it is easy for the unwary and inexperienced to produce code that simulates successfully [...]' follows immediately the sentence `In this regard, it is considered by some to be superior to Verilog'. This could mislead the reader to think that the second sentence applies specifically to VHDL. In reality it applies to Verilog as well.

I fixed this error. I assume that the flip-flop/latch pitfall doesn't apply to Verilog, but someone please tell me if I'm wrong. -- Heron 19:20, 14 Jul 2004 (UTC)
Actually, the flip-flop/latch pitfall applies to Verilog as well.

I an new to Wikipedia, and I didn't see the discussion page before I edited the statement inder the VHDL discussion. The line I saw today seemed to imply that VHDL could do testbench work, and that verilog was less capable in this regard. In fact, both are very successful at these tasks, so I changed the sentence to reflect this. Gordwait

Another misleading/confusing point on testbenches:

"It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench..."

This makes it sound like it's normal for a testbench to generate more VHDL code *when run* that then gets compiled...? Theoretically possible but I've never seen it. I propose the following edit which makes more sense in the context of real usage:

"It can read and write files on the host computer. Because of this general-purpose nature, it is possible to use VHDL to write a testbench..."

The real point of a testbench is that you get to use all the non-synthesizable features of the language to generate the stimuli and checks for your design.

192.91.75.29 18:52, 15 August 2007 (UTC)[reply]

Also: "However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL."

1. "in any other HDL" ? Drive strengths surely exist in Verilog (I have IEEE1364-2001 in front of me), accomplish the same thing, and are arguably more powerful (more levels of drive strengths)

2. "a very powerful simulation and debugging tool"...great, but no example of the benefit is given? Like the ability to detect conflicts on multiply driven nets...anything else? 192.91.75.29 18:59, 15 August 2007 (UTC)[reply]

Same thing? Depends...do the drive levels resolve to binary inputs or operations (e.g. simply things like transition & guard levels for single Base2 bit line)? Or are full 9-valued Base9 inputs or logic operations supported? The differences do need to be clarified. 69.23.124.142 (talk) 06:49, 18 December 2008 (UTC)[reply]

Hello World

I appreciate that the "Hello World" program is a tradition for languages but I don't really think it helps or adds anything to the article. I personally think that it just confuses matters as it doesn't really bear any relation to the way VHDL is used 99% of the time. Wouldn't it be better to replace it with an example of a simple testbench, or even something simple like a latch?


I agree with the statement to remove the Hello World example. It doesn't even run on the VHDL simulator that comes with my college textbook. Since this isn't really a computer language, but a design language, Hello World doesn't really fit. Bob/Paul

Another Example

 library IEEE;
 use IEEE.std_logic_1164.all;
 entity Shifter is
    port (
       CLK : in STD_LOGIC;
         D : in STD_LOGIC;
         Q : out STD_LOGIC
    );
 end Shifter;
 
 architecture behaviour of Shifter is
 signal rShift : STD_LOGIC_VECTOR(3 downto 0);
 begin
     process(CLK)
     begin
        if CLK'event and CLK='1' then
            rShift(3)<=D;
            rShift(2 downto 0)<=rShift(3 downto 1);
        end if;
     end process;
     Q <= rShift(0);
 end behaviour;

Anyway: It is definitely possible to write "standard" programs in VHDL (for example a sorting algorithm). What I don't know if tshifting thehis "program"-orientated features of the language are actually used often. Where I work we don't use VHDL much for verification, but mostly for synthesis. Can anyone give a comment how widespread and how extensive VHDL is used for verfication ?

I think this example is far more appropriate than the "hello world" example. - James Foster 11:31, 14 Jun 2005 (UTC)

I completely agree with all of the above. I changed the Hello World example to a latch. The above example is good, but it seems more like a queue than a shifter. Maybe if rShift were an output. But then why would you need Q as an output? I don't think the fibonacci example is the best example for this page either. Perhaps we could replace it with the above example? Or maybe a link to VHDL examples. Or a new Wikipedia article dedicated to VHDL code examples. Epachamo 20:52, 20 February 2006 (UTC)[reply]

I agree with that - the code above would basically act as a queue, from the looks of it. If you could write and read rShift you could use Q as 'carry out', if you were constructing a rotate-right function for a microprocessor... Mike1024 (t/c) 11:20, 31 March 2006 (UTC)[reply]
Actually I think I put this example there. I am not sure what you mean by "queue" (queue sounds to me like you mean a FIFO). This example simply takes the input D, and delays it by 4 clock cycles. This kind of construct is often called Shift_register (In this case serial in, serial out) ? This kind of construction is often used, if you want to "delay" a value by some clock cycles in a pipelined calculation. 84.154.43.11 19:04, 27 December 2006 (UTC)[reply]
What's the thought for examples on this section? Do you all only want 1 or 2 or would a few more make sense? Perhaps a counter example, or a small state machine? Or do you prefer to let the external links to VHDL docs provide the greater detail? Also, there is very little said about testbenches. Would it be a benefit to expand on that? (presumably testbench examples would be too long to include) jwilkinson 16:07, 20 April 2006 (UTC)[reply]

ASCII is seven bits, not eight bits

And by saying it is eight bits, it leads to confusion. Quoting the article:

"The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to match the full 8-bit ASCII definition, added the xnor operator, etc."

The ASCII article itself points out that ASCII is seven bits, and while there have been many 8-bit extensions over the decades (from myriad terminal makers and early microcomputers such as the Apple ][), and while the IBM PC's 8-bit character set became a de facto standard, there's no REAL standard for "8-bit ASCII." I read the IEEE 1076 article and saw no mention of ASCII, so I can only wonder if the author of the quoted sentence meant VHDL was extended to use the IBM PC or other 8-bit character set, or if it previously used only a part of the true 7-bit ASCII set and was extended to use all of it, or what.

Comment from Wesley J. Landaker: What VHDL '93 supports is ISO-8859-1; only printable characters are allowed to be used in the actual source (e.g. literal strings, identifiers); the character type itself can hold any value from 0x00-0xff, but they are always interpreted as ISO-8859-1 characters. There are efforts to make VHDL support something better, e.g. UTF-8, but nothing standardized.

Syntax in Fibonacci example

What is up with the end statements in the second example? "end entity Fibonacci;" should be just "end Fibonacci;" as in the first example. Likewise "end architecture Rcingham;" should just be "end Rcingham;", as a synthesis of the code will demonstrate. I'll change it now. ralian 02:29, 22 March 2006 (UTC)[reply]

Response to Ralian's note: Newer versions of the standard support full symmetry in keywords bounding longer blocks of VHDL code: 'entity' ends with 'end entity', 'architecture' with 'end architecture', etc. (It definitely makes analysis of longer files easier.) For compatibility with older versions of the standard, omission of 'entity', etc. at the end is allowed. Please do not use synthesis tools as argument for language discussions - they are (by definition) operating on small subset of the language. Jerry_K 20:22, 25 August 2006 (UTC)[reply]

Proposal to move VHSIC Hardware Description Language to VHDL

The following discussion is closed. Please do not modify it. Subsequent comments should be made in a new section.

I propose moving this page (VHSIC Hardware Description Language) to VHDL and making the former a redirect to the latter. My rationale is twofold: first, the language is almost universally referred to and known by its abbreviation VHDL rather than the long name for which it stands, and second, for the same rationale that the Wikipedia article on NASA is titled NASA rather than National Aeronautics and Space Administration (which is a redirect to NASA)—NASA is simply the more widely known and used name. Any objections?

—Muhandis 19:15, 24 September 2006 (UTC)[reply]

No objections from me, I agree with the move. Vadmium 01:15, 25 September 2006 (UTC)[reply]
Works for me. Seems it was moved back in April of this year too. — RevRagnarok Talk Contrib 11:16, 25 September 2006 (UTC)[reply]
The discussion above is closed. Please do not modify it. Subsequent comments should be made on the appropriate discussion page. No further edits should be made to this discussion.
The result of the request is rename

New examples

I have added some new examples (templates) to the VHDL page which i feel are important to understanding VHDL. However, the code is untested (full of syntax errors, i fear) and I am not a native English speaker so the new text might need some cleaning... I was also thinking about adding the RTL representation (i.e. an image) to each template. Would that be of any good? I could also add more examples, but the page is getting messy, so maybe we should start a new page for VHDL examples/templates? Furthermore, i have added a section called "getting started with VHDL" which i feel is important too, given the questions i see on the comp.lang.vhdl and comp.arch.fgpa newsgroups everyday. -- 83.249.212.91 17:11, 16 October 2006 (UTC) VHDL developer[reply]

I think it should be reverted because WP is not supposed to be a howto guide. And even more so if your examples haven't even been syntax checked. — RevRagnarok Talk Contrib 18:26, 14 October 2006 (UTC)[reply]
It is not a howto guide. It explains the templates, which is the difference between HDL and programming languages. I think they are very important for understanding the contecp. If you check the Verilog and System Verilog pages, you will notice pretty much the same examples there too. I agree that it is a little messy, but i would rather see it cleaned up than removed. Anyway, I have created images for the example code (yes, they compile just fine) and maybe adding the RTL view for each snippted would make it more understandable. I am still learnng WP and trying to figure out how to uploaded pictures to the page.... -- 83.249.212.91 17:11, 16 October 2006 (UTC)[reply]
I removed the new examples. All of them are already present in the code examples above. Michagal 16:47, 16 April 2007 (UTC)[reply]

History

Is it possible to insert some dates in the History chapter? I think it would be interesting to see how old the language is and that is still used today. Theups 19:41, 30 November 2006 (UTC)[reply]

Examples and "end" statements

I just tweaked the examples because there were a few edits previously. I verified every one just now with ModelSim PE 6.2a with my usual command line of vcom -2002 -explicit -lint -source. I know the architecture / entity at the end is optional, but cleaner and easier to debug. Additionally, since this is looking like a small primer, I think it is better to be as verbose as possible in the intro, if somebody becomes more experienced on their own, they learn things like "only an idiot would actually synthesize the AND gate component shown here" or "any engineer who does port mapping by position buys lunch." — RevRagnarok Talk Contrib 14:48, 4 December 2006 (UTC)[reply]

Is it wise, though, for this article to be written as a primer? Compared to C++, which seems to me to be a well-written language article, this one is light on information about the language and heavy on how-tos. For one, the "Getting started with VHDL" section needs to be re-written or deleted, I think. There probably shouldn't be much sample code, either. A few very short examples in context, maybe, but not a series of stand-alone tutorials. I understand the desire to teach the language, but I don't think it's encyclopedic.
Changes I believe should be made:
  • Expansion of the Verilog comparison
  • Clarification of the difference between VHDL and a software programming language
  • Expansion/clarification of the difference between synthesizable code and simulation-only code
  • Clearer, more specific differences between '87, '93, etc.
  • Revision/deletion of "Getting started" section (a short list of leading tools is one thing, but this appears to be a "recommended tool flow", which may vary greatly from company to company)
  • Revision/reorganization/trimming of "Code examples" section (see above)
Comments? -- Fru1tbat 15:49, 4 December 2006 (UTC)[reply]
I agree on all points. Back in October (above) I said there was too much howto. However, if it's gonna be there, I'd like it to be correct. I'd recommend you move your list into a {{todo}} — RevRagnarok Talk Contrib 18:17, 4 December 2006 (UTC)[reply]
I agree (but see also my post below). But note that the "getting started" section isnt really about tools, companies or "flows". its about how to get started without paying $$$. For example, if GHDL was more stable, I would have included that too. 83.254.148.19 22:38, 13 December 2006 (UTC)[reply]
IMHO, there is too much howto, and not enough language description. I came looking for information about VHDL, namely something that would make synthesizable VHDL (or Verilog) not considered a functional programming language. When I read through the mux template examples, some of the intention isn't clear...for instance, why do all of your case statements have a "when others" (or equiv.) clause instead of creating a case for each of the possible select inputs? The answer is it depends on the signal type (bit_vector or std_logic_vector). In the case of bit_vector, since each of the bits can take the values (0,1,X), a case would have to be written for each one for the case statement to be complete. In the case of std_logic_vector, each bit can take the values (U,X,0,1,Z,W,H,L,-), which ends up being a lot of cases! If a case isn't written for each of the values of the bits, the synthesis tools will report and incomplete case statement. Additionally, these extra cases may not be realizable in hardware (Xilinx and Altera FPGAs can't represent U, X, Z, W, H, L, - in the fabric) so clutter up the code. So the "when others" clauses satisfy the desires of the synthesis tools (explicitly cover ever value of the bit type) while avoiding unimplementable code (bit values that can't be synthesized in hardware). Wingnut2k7 (talk) 15:38, 7 December 2008 (UTC)[reply]


I don't completely agree with RevRagnarok about the style. I cant understand how adding extra words to your code makes it "cleaner and easier to debug". It is the same code, with the same functionality, isn't it? On the contrary, when I review code from designers, I see the optional stuff in jr. engineers code, while the more experienced ones strictly avoid them. VHDL is verbose enough as it is, why do you want to make it even more verbose? Maybe at the end of the day, this is a matter of taste. In that case, I don't think you should force your style on people. Think if someone changed all C code on wikipedia from GNU to K&R indentation :(
Of course, there are situations such as port-mapping where the shorter style is unsafe. I agree with you on this one but this is because it can produce bad code, its not a matter of style anymore.
Also, about the examples... I took some time to synthesize every design with Synplify and check the result. They are all ok. But maybe we should create a new page that compares different HDLs (VHDL, verilog etc) instead? leave some basic stuff here and more the rest of the examples to this new page? 83.254.148.19 22:38, 13 December 2006 (UTC)[reply]

TODO List

After some preliminary comparisons of VHDL and Verilog, I think really the biggest difference is the type system.

  • Complete (complex) type system in VHDL
  • Only language defined types in Verilog

Actually that is one (only?) reason why one might argue that VHDL is superior to Verilog. Even when you write code which is intended for synthesis, I think the lack of a type system in Verilog is severe.

For example: If you build several modules which all connect to the same type of "command bus", you can specify the signals for the command bus in a "record" composite type in VHDL. Then each module gets an input signal of this composite type and that's it.

If you then later change the exact way the command bus works you can simply modify the type definition for the command bus instead of editing each and every module. Of course you might be able to do the same in Verilog by extensively using "include" directives, but this seems to be really ugly... —The preceding unsigned comment was added by 84.154.43.11 (talk) 19:23, 27 December 2006 (UTC).[reply]

just checked the external links. looks more like spam to me (specially the recent additions). Here are my suggestions:

remove:

  • Designers Guide to VHDL (more or less spam)
I'm going to have to own up to this as I think I added it a while ago (and just recently started reading COI guides etc). I do work for the Co. in question, however I still believe it's a valid and useful resource and we're not getting any Google karma from the link. Anyway I'm the IT guy, not a VHDL user so take a look, if you don't agree then wipe the link. Spidge 09:38, 24 September 2007 (UTC)[reply]
  • Qualis Design Corporation (crap. If its a must, Hardi have a more popular one free of charge)
Linking to a tutorial site might be ok, but an individual link to a quick reference cards is probably inappropriate --Fru1tbat
  • FPGA FAQ (people dont know how to google? and we are adding the newsgroup itself)
Eh, I think this one is ok (though I might reword the link text)
  • '99 bottles of beer' in VHDL (this is really stupid)
  • PN Sequence Generator VHDL example see (where is the external link?)
  • HDL Designer Series, ModelSim and Precision Synthesis (spam!)
  • Signs (company is already dead)
  • Xilinx and Altera (see below)
(agreed on the rest) --Fru1tbat

keep:

  • GHDL (free is good)
  • VHDL emacs mode (seems harmless)
I'm not sure if these belong or not. Yes, they're relevant to the language, but they're not informative, per se, and they set a bad precedent (addition of useful software tools, etc). --Fru1tbat

add:

  • comp.arch.fpga and comp.lang.vhdl


point to wiki article instead:

  • opencores
  • all FPGA manufactures : Xilinx, Altera, Lattice, QuickLogic, Actel. (more fair to mention them all than just a few. but better to link to their wiki page than their site)
  • since we are adding all these FPGA stuff, we probably should mention ASIC too. or maybe digital design as whole?
  • maybe also the tool vendors if we cant avoid it: Mentor, Aldec, Synopsys , Magma, Cadence and Synplicity.

what do you think? 83.254.183.147 20:16, 5 January 2007 (UTC)[reply]

Yeah, the list is way too long. In my opinion, when you have multiple sub-categories, you have far too many links. The article has almost become a VHDL user's resource, not an encyclopedia article (as I've alluded to before, but haven't had time to tackle). Furthermore, Wikipedia is not a repository of links. I would recommend that major FPGA vendors be left to the FPGA article. The VHDL article should not be a guide to FPGA design flow. It should be an article on the language. I've inserted some other specific in-line comments above (I've taken the liberty of re-doing the bullets so it won't break for inline comments).
As for ASICS, etc, the more appropriate article for that might be Electronic design automation. I don't keep track of that one, though (yet). It looks like it could use some work, but it's the better starting place for the bigger picture.
--Fru1tbat 21:07, 5 January 2007 (UTC)[reply]
After further consideration, I've decided to go ahead and be bold and remove most of the external links that appear to violate WP:EL. For now, I've removed everything that's dead, not actually an external link, purely commercial/vendor oriented, a "designer's resource" more than a generally informative page, or a minor software resource. I left one of the examples for now, but I think it might be better to link to a tutorial-like site that provides multiple examples, instead of just a single (lengthy) example. --Fru1tbat 21:42, 5 January 2007 (UTC)[reply]
nice job. The only thing I miss is the OpenCores refrence. UART example is actually used on comp.lang.vhdl as a _complex_ reference design.
while we are removing spam... i will remove the semi-spam from the "getting started" section83.254.183.147 22:56, 6 January 2007 (UTC)[reply]

Waveform and Vector Exchange Specification

The following discussion is closed. Please do not modify it. Subsequent comments should be made in a new section.

I've found Waveform and Vector Exchange Specification as new pagea nd it seesm to refer here. Please check whether it can be merged here. --Tikiwont 08:41, 23 April 2007 (UTC)[reply]

The discussion above is closed. Please do not modify it. Subsequent comments should be made on the appropriate discussion page. No further edits should be made to this discussion.

Needs to rename back to VHDL

There was a discussion in September 2006 (see above) to rename this article to VHDL, and consensus was to move. But then it was renamed back to VHSIC Hardware Description Language on 29-Jan-08, apparently without discussion. I intend to rename it back to "VHDL" shortly because that was the consensus back in 2006, and reason - that "VHDL" is the far more common designation - is still valid. Peter Ballard (talk) 07:01, 2 June 2008 (UTC)[reply]

The following discussion is an archived discussion of the proposal. Please do not modify it. Subsequent comments should be made in a new section on the talk page. No further edits should be made to this section.

moved Consensus to rename back to previous consensus. DMacks (talk) 18:51, 16 June 2008 (UTC)[reply]

Requested move

I propose this page be renamed back to "VHDL" because:

  1. "VHDL" is what it is commonly known as.
  2. There was a discussion in September 2006 (see above), and consensus was to rename it to VHDL
  3. It was renamed to "VHSIC Hardware Description Language" without discussion or consensus in January 2008.

Peter Ballard (talk) 02:50, 9 June 2008 (UTC)[reply]

Survey

Discussion

The above discussion is preserved as an archive of the proposal. Please do not modify it. Subsequent comments should be made in a new section on this talk page. No further edits should be made to this section.

Too many code examples

I think this article has way too many code examples. I know this is well intentioned, but this is an encyclopedia, not a software manual. The article should concentrate on verbally describing VHDL, its history, its differences (and similarities) to other HDL languages, and links to resources. p.s. I've noticed a similar problem on other software languages' pages. Peter Ballard (talk) 11:45, 11 August 2008 (UTC)[reply]

Removed weasel sentences

The weasel nonsense about VHDL being supposedly superior (or not or whatever) to Verilog has been around and tagged long enough so I just got rid of it. If someone can provide a NPOV comparison, then cool. And no, I'm not a Verilog fan. Jiri Svoboda (talk) 13:02, 21 February 2009 (UTC)[reply]

Retrieved from "https://en.wikipedia.org/w/index.php?title=Talk:VHDL&oldid=272257071"