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Symposia on VLSI Technology and Circuits

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Symposium on VLSI Circuits is an international conference on semiconductor circuits. It brings together managers, engineers, and scientists from industry and academia around the world to discuss challenges in Very-large-scale integration (VLSI) of circuits. The Symposium was established in 1987[1] and takes place once a year around the middle of June at locations alternating between Kyoto, Japan and Honolulu, USA. The Symposium on VLSI Circuits is held in conjunction with the Symposium on VLSI Technology[2], thereby offering an opportunity to interact and synergize on topics of joint interest, spanning the range from process technology to systems-on-chip [3] [4] [5] [6] [7]. Beside regular presentations of technical papers, the Symposium comprises short courses, panel sessions, and invited talks conducted by experts in the field from both Industry and Academia.

Sponsors

The Symposium on VLSI Circuits is sponsored by the IEEE Solid-State Circuits Society and the Japan Society of Applied Physics in cooperation with the Institute of Electronics, Information and Communication Engineers and the IEEE Electron Devices Society. Extended versions of selected papers from the Symposium are regularly published once a year in a special Issue of the IEEE Journal of Solid-State Circuits[8].

Symposium 2012

The 2012 Symposium on VLSI Circuits was held at the Hilton Hawaiian Village, Honolulu, Hawaii on June 13–15. Joint circuit and technology focus sessions were offered in the following special topics of mutual interest[9] [10] [11]:

  • Memory (emerging non-volatile memory, advanced SRAM, embedded memories) [12] [13] [14]
  • 3-D System Integration[15]
  • Design in Scaled Technologies
  • Design Enablement in Scaled CMOS

The Symposium was be preceded by two full-day short courses. In total, around 100 technical papers were presented on innovations and advancements in the field of VLSI circuit design.[16]

Symposium 2013

  • The 2013 Symposium on VLSI Circuits will be held in Kyoto, Japan between 2013-06-11 and 2013-06-14.
  • The dead line for paper submissions is 2013-01-21.
  • Author guide lines will become available at http://vlsisymposium.org/symposia.html

References

  1. ^ The Beginnings of the Symposium on VLSI Circuits (JSSC 1997)
  2. ^ Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium (ElectroIQ 2012)
  3. ^ VLSI Symposium eyes 65-nm logic (EETIMES 2003)
  4. ^ VLSI papers weigh 65 nm, new circuits (EETIMES 2004)
  5. ^ VLSI SYMPOSIUM REPORT: Chipmakers, consortia reveal HK+MG integration (ElectroIQ 2007)
  6. ^ Report from VLSI Symposium: Planar CMOS to 22nm, at most (ElectroIQ 2008)
  7. ^ Report from the VLSI Symposium: Less spirited, still informative (ElectroIQ 2009)
  8. ^ Journal of Solid-State Circuits (JSSC)
  9. ^ VLSI confabs call for mutual interest topics (EETIMES 2011)
  10. ^ Attend joint sessions at VLSI Technology and Circuits (ElectroIQ 2012)
  11. ^ VLSI confab brings technology, circuits to the fore (EETIMES 2012)
  12. ^ Emerging Memories Take Stage at VLSI Symposium (SMD 2012)
  13. ^ IMEC to detail memristor progress at VLSI Symposia (EETIMES 2012)
  14. ^ Four Macronix Papers Selected for 2012 Symposium on VLSI Technology (DigiTimes 2012)
  15. ^ TI details TSV integration in 28-nm CMOS (EETIMES 2012)
  16. ^ MediaTek Papers Selected for Presentation at 2012 Symposium on VLSI Circuits (PR Newswire 2012)

Additional information

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