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Saraju Mohanty

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Saraju Mohanty
Prof. Saraju Mohanty in 2012
Born
Odisha, India
NationalityUnited States
Alma materUniversity of South Florida (USF), Tampa
Indian Institute of Science (IISc), Bangalore
Orissa University of Agriculture and Technology (OUAT), Bhubaneswar
Occupation(s)Professor, author, scientist, computer engineer
Known forMixed-Signal Systems, Nanoelectronics Systems, Metamodeling, Design for X, High-level synthesis, Hardware-assisted digital watermarking
Notable workNanoelectronic Mixed-Signal System Design, McGraw-Hill, 2015, ISBN 978-0071825719
SpouseDr. Uma Choppali
HonorsPROSE Award for best textbook in Physical Sciences & Mathematics in 2016


Toulouse Scholars Award from UNT in 2016-17

President's Scout Award in 1988
Websitewww.smohanty.org

Saraju Mohanty is an American professor of the Department of Computer Science and Engineering, and the Director of the NanoSystem Design Laboratory , at the University of North Texas in Denton, Texas.[1][2] Professor Mohanty is a researcher in the areas of "Low-Power High-Performance Nanoelectronics Systems" and "hardware-assisted Digital watermarking".[3] He has made significant research contributions to analogue electronics and mixed-signal integrated circuit computer-aided design and Electronic design automation, nanoelectronic technology based high-level synthesis, and hardware-assisted digital watermarking. He has held the Chair of the IEEE Computer Society's Technical Committee on Very Large Scale Integration since September 2014.[4][5] He holds 4 US patents in the areas of his research. Professor Mohanty has published 200 papers and 3 books.[6][7][8]

Education

Saraju Mohanty started his schooling at Lodhachua, Nayagarh, Odisha. After graduating from Badagada Government High School, Bhubaneswar in 1988, Mohanty completed a 10+2 Science degree from Rajdhani College, Bhubaneswar in 1990. Whilst at high school he was a quite active and recognized member of The Bharat Scouts and Guides. He received his bachelor's degree (with Honors) in electrical engineering from the College of Engineering and Technology, Bhubaneswar, Orissa University of Agriculture and Technology, in 1995.[9][10]

In 1999 Mohanty completed a master's degree in engineering in Systems Science and Automation from the Indian Institute of Science in Bangalore, India. His master's thesis mentors were Professor K. R. Ramakrishnan[11] and Professor Mohan S. Kankanhalli[12] with whom he co-authored his first peer-reviewed paper.[13] Mohanty earned a Ph.D. in computer engineering from the University of South Florida in 2003. His Ph.D. mentor was Professor N. Ranganathan (IEEE Fellow and AAAS Fellow).[14][15][16]

Notable scientific contributions

Contributions to analog electronics and mixed-signal circuits

Mohanty has worked on design space exploration and optimization of nanoelectronic integrated circuits. The key feature of these design flows is the need for only two manual layout (or physical design) iterations which saves significant design effort. These ultra-fast design flows rely on accurate metamodels of the analog and mixed-signal circuit components. His research significantly advances the state-of-the art in Design for Excellence (DfX) or Design for X, such as Design for Variability (DfV) and Design for Cost (DfC).[17]

Contributions to high-level synthesis

Mohanty is a contributor to nanoscale CMOS or nanoelectronic technology based high-level synthesis (HLS) or architecture-level synthesis.[18][19][20] His nanoelectronic-based High-level synthesis techniques addresses the issue of process variations, the primary issue of nanoelectronic technology, during the high-level synthesis itself before the digital design moves to the detailed and lower levels of design abstractions, such as logic-level or transistor-level.[21]

Contributions to Digital watermarking and Digital rights management (DRM)

Mohanty has worked on the Secure Digital Camera (SDC) for real-time Digital rights management (DRM) at the source end of the multimedia content. The SDC has quite diverse applications where still image or video digital cameras are needed, such as secure Digital Video Broadcasting, secure Video Surveillance, electronic passport, and identity card processing. The secure digital camera (SDC) has been well-adopted by various researchers worldwide.[22][23][24]

Professional leadership

Editorial board

Conference Chairmanship

  • Steering Committee Chair, IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)[33]
  • Steering Committee Vice-Chair, IEEE-CS Symposium on VLSI (ISVLSI)[34]
  • Steering Committee Vice-Chair, OITS International Conference on Information Technology (ICIT)[35]

Professional membership

Awards and honors

Patents

  • Methodology for Nanoscale Technology based Mixed-Signal System Design, US Patent Number: 9,053,276.
  • Intelligent Metamodel Integrated Verilog-AMS for Fast and Accurate Analog Block Design Exploration, US Patent Number: 9,026,964.
  • Apparatus and Method for Transmitting Secure and/or Copyrighted Digital Video Broadcasting Data Over Internet Protocol Network, US Patent Number: 8,423,778.
  • Methods and Devices for Enrollment and Verification of Biometric Information in Identification Documents, US Patent Number: 8,058,972.

Selected Publications

Consumer Electronic Systems for Smart Cities

  • Swing-Pay: One Card Meets All User Payment and Identity Needs, IEEE Consumer Electronics Magazine, Volume 7, Issue 1, January 2017, pp. 82--93.
  • Pay-Cloak: A Biometric Back Cover for Smartphone with Tokenization Principle for Cashless Payment, IEEE Consumer Electronics Magazine, Volume 7, Issue 2, April 2017, pp. 78--88.
  • Design of a High-Performance System for Secure Image Communication in the Internet of Things (Invited Paper), IEEE Access Journal, Volume 4, 2016, pp. 1222--1242.
  • Everything You wanted to Know about Smart Cities, IEEE Consumer Electronics Magazine, Volume 6, Issue 3, July 2016, pp. 60--70.

Low-Effort Methodologies for Mixed-Signal System Design

  • Process Variation Analysis and Optimization of a FinFET based VCO, IEEE Transactions on Semiconductor Manufacturing (TSM), 2017.
  • Fast Layout Optimization through Simple Kriging Metamodeling: A Sense Amplifier Case Study, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 22, Issue 4, April 2014, pp. 932--937.
  • Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs, IEEE Transactions on Semiconductor Manufacturing (TSM), Volume 27, Issue 1, February 2014, pp. 22--31.
  • Geostatistical-Inspired Fast Layout Optimization of a Nano-CMOS Thermal Sensor, IET Circuits, Devices & Systems (CDS), Volume 7, No. 5, September 2013, pp. 253--262.
  • A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits, IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 25, No. 1, February 2012, pp. 26--36.
  • Design of Parasitic and Process Variation Aware RF Circuits: A Nano-CMOS VCO Case Study, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 17, No. 9, September 2009, pp. 1339-1342.

Hardware-Assisted Security

  • TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.
  • Low-Cost Security Aware HLS Methodology, IET Computers & Digital Techniques (CDT), Volume 11, Issue 2, March 2017, pp. 68--79.
  • VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking, IET Computers & Digital Techniques (CDT), September 2007, Volume 1, Issue 5, pp. 600-611.
  • A Dual Voltage-Frequency VLSI Chip for Image Watermarking in DCT Domain, IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 53, No. 5, May 2006, pp. 394-398.
  • A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 13, No. 8, August 2005, pp. 1002-1012.

Energy-Efficient Hardware Design

  • DOE-ILP Assisted Conjugate-Gradient Optimization of High-κ/Metal-Gate Nano-CMOS SRAM, IET Computers & Digital Techniques (CDT), Vol. 6, No. 4, July 2012, pp. 240--248.
  • ULS: A Dual-Vth/High-K Nano-CMOS Universal Level Shifter for System-Level Power Management, Special Issue on Design Techniques for Energy Harvesting, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 6, No. 2, June 2010, pp. 8:1--8:26.
  • Simultaneous Scheduling and Binding for Low Gate Leakage Nano-Complementary Metal-Oxide-Semiconductor Datapath Circuit Behavioural Synthesis, IET Computers & Digital Techniques (CDT), March 2008, Volume 2, Issue 2, pp. 118-131.
  • ILP Models for Simultaneous Energy and Transient Power Minimization during Behavioral Synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 1, January 2006, pp. 186-212.
  • Simultaneous Peak and Average Power Minimization during Datapath Scheduling, IEEE Transactions on Circuits and Systems Part I (TCAS-I), Vol. 52, No. 6, June 2005, pp. 1157-1165
  • A Framework for Energy and Transient Power Reduction during Behavioral Synthesis, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 12, No. 6, June 2004, pp. 562-572

Ph.D. Dissertations Supervised

  • New Frameworks for Secure Image Communication in the Internet of Things (IoT)
  • Analysis and Optimization of Graphene FET Based Integrated Circuits
  • Geostatistical Inspired Metamodeling and Optimization of Nanoscale Analog Circuits
  • Secure and Energy Efficient Execution Frameworks Using Virtualization and Light-Weight Cryptographic Components
  • Layout-Accurate Ultra-Fast System Level Design Exploration Through Verilog-AMS
  • Metamodeling-Based Fast Optimization of Nanoscale AMS-SoCs
  • Process-Voltage-Temperature Aware Nanoscale Circuit Optimization
  • Variability Aware Low-Power Techniques for Nanoscale Mixed-Signal Circuits

References

  1. ^ The University of North Texas, Dept. of Computer Science and Engineering, NanoSystem Design Laboratory, http://nsdl.cse.unt.edu/
  2. ^ The University of North Texas, Dept. of Computer Science and Engineering, http://www.cse.unt.edu/site/node/91
  3. ^ Research Interests, Prof. Saraju Mohanty, http://www.cse.unt.edu/~smohanty/Research.html
  4. ^ Dr. Saraju Mohanty Serves as the Chair of the Technical Committee on Very Large Scale Integration (TCVLSI), https://facultysuccess.unt.edu/dr-saraju-mohanty-serves-chair-technical-committee-very-large-scale-integration-tcvlsi
  5. ^ Technical Committee on VLSI, http://www.computer.org/portal/web/tandc/tcvlsi
  6. ^ ResearchGate - Saraju Mohanty, http://www.researchgate.net/profile/Saraju_Mohanty
  7. ^ Google Scholar List - Saraju Mohanty, https://scholar.google.com/scholar?hl=en&q=saraju+mohanty
  8. ^ DBLP - Saraju Mohanty, http://dblp.uni-trier.de/pers/hd/m/Mohanty:Saraju_P=.html
  9. ^ CET Bhubaneswar observes Annual Alumni Meet, http://www.odishanewsinsight.com/events/cet-bhubaneswar-observes-annual-alumni-meet/, December 31, 2015.
  10. ^ Unitary University Status For CET Demanded, The Pioneer, http://www.dailypioneer.com/state-editions/bhubaneswar/unitary-university-status-for-cet-demanded.html, Thursday, 31 December 2015.
  11. ^ S. P. Mohanty, "Watermarking of Digital Images", Master of Engineering in System Science and Automation Thesis, Indian Institute of Science, Bangalore, January 1999, http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.10.1673&rep=rep1&type=pdf
  12. ^ "Past Postdocs and Graduated Students". Retrieved 8 August 2016.
  13. ^ S. P. Mohanty, K. R. Ramakrishnan, and M. S. Kanakanhalli, "A Dual Watermarking Technique for Images", in Proceedings of the 7th ACM International Multimedia Conference (ACMMM) (Vol. 2), pp.49-51, 1999.
  14. ^ S. P. Mohanty, "Energy and Transient Power Minimization During Behavioral Synthesis", Ph.D. Dissertation, Department of Computer Science and Engineering, University of South Florida, 2003, http://etd.fcla.edu/SF/SFE0000129/SarajuDissertationFinal.pdf
  15. ^ Computer Science Tree, N. Ranganathan, University of South Florida, http://academictree.org/computerscience/tree.php?pid=416222
  16. ^ Nagarajan “Ranga” Ranganathan, Department of Computer Science and Engineering, University of South Florida, Tampa, FL 33620,http://www.usf.edu/engineering/cse/documents/ranganathan-cv.pdf
  17. ^ DFX for Nanoelectronic Embedded Systems, Keynote Address at First IEEE Sponsored International Conference on Control, Automation, Robotics and Embedded System, CARE-2013, http://care.iiitdmj.ac.in/Keynote_Speakers.html.
  18. ^ Saraju Mohanty and Elias Kougianos, "Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis", in Proceedings of the 20th International Conference on VLSI Design, pp. 577-582, 2007.
  19. ^ Mohanty, S. P.; Gomathisankaran, M.; Kougianos, E. (2014). "Variability-Aware Architecture Level Optimization Techniques for Robust Nanoscale Chip Design". Elsevier Computers and Electrical Engineering Journal. 40 (1): 168–193. doi:10.1016/j.compeleceng.2013.11.026.
  20. ^ Chen, Y.; Wang, Y.; Takach, A.; Xie, Y. "Parametric Yield Driven Resource Binding in High-Level Synthesis with Multi-Vth Vdd Library and Device Sizing". Journal of Electrical and Computer Engineering. 2012: 105250.
  21. ^ "Unified Challenges in Nano-CMOS High-Level Synthesis", Invited Talk, 22nd IEEE International Conference on VLSI Design, 2009.
  22. ^ Thomas Winkler, Adam Erdelyi, and Bernhard Rinner, "TrustEYE M4: Protecting the Sensor--not the Camera", in Proceedings of the International Conference on Advanced Video and Signal Based Surveillance, 2014.
  23. ^ S. D. Roy, X. Li, Y. Shoshan, A. Fish, and O. Yadid-Pecht, "Hardware Implementation of a Digital Watermarking System for Video Authentication". IEEE Transactions on Circuits and Systems for Video Technology. 23 (2), 2013, pp. 289–301.
  24. ^ C. -T. Yen, T. Wu, M. -H. Guo, C. -K. Yang, and H. -C. Chao, "Digital product transaction mechanism for electronic auction environment". IET Information Security. 4 (4), 2010, pp. 248–257.
  25. ^ a b UNT Professor Receives Editorial Appointments, Recognition, http://engineering.unt.edu/unt-professor-receives-editorial-appointments-recognition
  26. ^ IEEE Consumer Electronics Magazine Editorial Board, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7450780
  27. ^ IEEE Consumer Electronics Magazine, http://ieeexplore.ieee.org/xpl/aboutJournal.jsp?punumber=5962380
  28. ^ IEEE Consumer Electronics Magazine, http://cesoc.ieee.org/publications/ce-magazine.html
  29. ^ VLSI Circuits and Systems Letter (VCAL) -- Editorial Board, https://www.computer.org/web/tcvlsi/editorial-board
  30. ^ IEEE TCAD Editorial Board, http://ieee-ceda.org/publications/tcad/editorial-board
  31. ^ ACM JETC Editorial Board, http://jetc.acm.org/editorial_board.cfm
  32. ^ IET CDS Editorial Board, http://digital-library.theiet.org/journals/iet-cds/editorial-board
  33. ^ IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), http://www.ieee-inis.org/
  34. ^ IEEE-CS Symposium on VLSI (ISVLSI), http://www.isvlsi.org/
  35. ^ International Conference on Information Technology (ICIT), http://www.oits-icit.org/
  36. ^ Saraju P. Mohanty, ACM Senior Member, United States – 2010, http://awards.acm.org/award_winners/mohanty_2241263.cfm
  37. ^ Chair TCVLSI Bio, https://www.computer.org/cms/technical-activities/Technical-Committees/Elections/tcvlsi/2016/mohanty-2016-tcvlsi-biosketch-and-position-statement.pdf
  38. ^ Peter Corcoran, Welcome to Our Incoming Editor-in-Chief, CE Magazine Editorial, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7539241
  39. ^ Technical & Conferences Activities Board -- Technical Committees -- Technical Committee on VLSI, http://www.computer.org/web/tandc/tcvlsi
  40. ^ Dr. Saraju Mohanty Serves as the Chair of the Technical Committee on Very Large Scale Integration (TCVLSI), http://www.cse.unt.edu/site/node/678
  41. ^ 2016 PROSE Award Winners, https://proseawards.com/winners/2016-award-winners/#body
  42. ^ Saraju Mohanty wins McGraw-Hill textbook award, https://facultysuccess.unt.edu/faculty-awards/saraju-mohanty-wins-mcgraw-hill-textbook-award
  43. ^ Engineering Professor Receives Awards, http://engineering.unt.edu/engineering-professor-receives-awards
  44. ^ Salute to Faculty Excellence 2016 Winners, http://facultysuccess.unt.edu/salute-faculty-excellence-2016-winners-0
  45. ^ ISVLSI 2015, http://www.eng.ucy.ac.cy/theocharides/isvlsi15/
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