Jump to content

IMPLY gate

From Wikipedia, the free encyclopedia

This is an old revision of this page, as edited by 152.105.62.50 (talk) at 08:36, 31 July 2023 (format truth table). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Input
A   B
Output
A → B
0 0 1
0 1 1
1 0 0
1 1 1

The IMPLY gate is a digital logic gate that implements a logical conditional.

Symbols

There are two symbols for IMPLY gates: the traditional symbol and the IEEE symbol. For more information see Logic gate symbols.

Traditional IMPLY Symbol IEEE IMPLY Symbol

The logic symbol → can be used to denote IMPLY in algebraic expressions.

See also