This is an old revision of this page, as edited by 99Electrons(talk | contribs) at 07:32, 9 March 2019(There's no point in adding a navigation template that doesn't even include a link to this article). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.
Revision as of 07:32, 9 March 2019 by 99Electrons(talk | contribs)(There's no point in adding a navigation template that doesn't even include a link to this article)
Scalable POWERparallel (SP) is a series of supercomputers from IBM. SP systems were part of the IBM RISC System/6000 (RS/6000) family, and were also called the RS/6000 SP. The first model, the SP1, was introduced in February 1993, and new models were introduced throughout the 1990s until the RS/6000 was succeeded by eServer pSeries in October 2000. The SP is a distributed memory system, consisting of multiple RS/6000-based nodes interconnected by an IBM-proprietary switch called the High Performance Switch (HPS). The nodes are clustered using software called PSSP, which is mainly written in Perl.
ASCI White is a 512-node system with a peak performance of 12.3TFLOPS. It was installed at the LLNL in 2001 as part of ASCI, and was ranked #1 in the Top500 List from November 2000 to November 2001.
Seaborg, at the Lawrence Berkeley National Laboratory, was ranked as the fifth fastest supercomputer in the world when it debuted in the June 2003 edition of the Top500 List. From a peak performance of 9.98TFLOPS, it obtained 7.30TFLOPS on the LINPACK benchmark.[3]
