IBM Scalable POWERparallel

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Scalable POWERparallel (SP) is a series of supercomputers from IBM. SP systems were part of the IBM RISC System/6000 (RS/6000) family, and were also called the RS/6000 SP. The first model, the SP1, was introduced in February 1993, and new models were introduced throughout the 1990s until the RS/6000 was succeeded by eServer pSeries in October 2000. The SP is a distributed memory system, consisting of multiple RS/6000-based nodes interconnected by an IBM-proprietary switch called the High Performance Switch (HPS). The nodes are clustered using software called PSSP, which is mainly written in Perl.

Computer scientist Marc Snir was awarded the Seymour Cray Computer Engineering Award by the Institute of Electrical and Electronics Engineers in 2013 for his contributions to supercomputing, which included his work on the SP.[1]

Notable systems[edit]

Nodes[edit]

POWER1-based[edit]

Model # of CPUs CPU CPU MHz Cache Memory Introduced Discontinued
SP1 1 POWER1++ 62.5 None 64 to 256 MB 1993-02-02 1994-12-16

POWER2-based[edit]

Model # of CPUs CPU CPU MHz L2 Cache Memory Introduced Discontinued
Thin 1 1 POWER2 66 ? 64 to 512 MB 1995-08-22 1996-12-20
Thin 2 ? ? 1997-06-27
Wide 1 ? 64 MB to 2 GB 1996-12-20
Wide 2 77 ? ? 1997-06-27

PowerPC 604-based[edit]

Model # of CPUs CPU CPU MHz Cache Memory Introduced Discontinued
High 1 2, 4, 6, 8 PowerPC 604 112 ? ? 1996-07-23 1998-01-08
High 2 PowerPC 604e 200 ? ? 1997-08-26 1998-04-21
332 Thin 2, 4 332 ? ? 1998-04-21 2000-12-29
332 Wide ? ?

P2SC-based[edit]

Model # of CPUs CPU CPU MHz Cache Memory Introduced Discontinued
160 Thin 1 P2SC 160 ? ? 1997-10-06 1998-04-21
Thin P2SC 120 ? ? 1996-10-08
Wide P2SC 135 ? ?

POWER3-based[edit]

Model # of CPUs CPU CPU MHz L2 Cache Memory Introduced Discontinued
POWER3 High 2, 4, 6, 8 POWER3 222 ? ? 1999-09-13 2000-12-29
POWER3 High POWER3-II 375 ? ? 2000-07-18 2002-12-27
POWER3 Thin 1, 2 POWER3 200 ? ? 1999-09-01 2000-06-30
POWER3 Thin POWER3-II 375 ? ? 2000-02-07 2003-04-08
POWER3 Thin 450 ? ? 2002-01-22
POWER3 Wide 1, 2 POWER3 200 ? ? 1999-02-01 2000-06-30
POWER3 Wide 2, 4 POWER3-II 375 ? ? 2000-02-07 2003-04-08
POWER3 Wide 2, 4 450 ? ? 2002-01-22

See also[edit]

References[edit]

  1. ^ "Marc Snir: 2013 Seymour Cray Award Recipient". IEEE Computer Society.
  2. ^ "SP2/512". TOP500 Supercomputer Sites. Retrieved 2 January 2019.
  3. ^ "Seaborg - SP Power3 375 MHz 16 way". TOP500 Supercomputer Sites. Retrieved 2 January 2019.

External links[edit]