Message Signaled Interrupts
Message Signaled Interrupts (MSI) are a method of signaling interrupts, using special in-band messages to replace traditional out-of-band signals on dedicated interrupt lines. While message signaled interrupts are more complex to implement in a device, they have some significant advantages over pin-based out-of-band interrupt signalling, such as improved interrupt handling performance. This is in contrast to traditional interrupt mechanisms, such as the legacy interrupt request (IRQ) system.
Message signaled interrupts are supported in PCI bus since its version 2.2, and in later available PCI Express bus. Some non-PCI architectures also use message signaled interrupts.
Overview
[edit]Traditionally, a device has an interrupt line (pin) which it asserts when it wants to signal an interrupt to the host processing environment. This traditional form of interrupt signalling is an out-of-band form of control signalling since it uses a dedicated path to send such control information, separately from the main data path. MSI replaces those dedicated interrupt lines with in-band signalling, by exchanging special messages that indicate interrupts through the main data path. In particular, MSI allows the device to write a small amount of interrupt-describing data to a special memory-mapped I/O address, and the chipset then delivers the corresponding interrupt to a processor.[1][2][3]
A common misconception with MSI is that it allows the device to send data to a processor as part of the interrupt. The data that is sent as part of the memory write transaction is used by the chipset to determine which interrupt to trigger on which processor; that data is not available for the device to communicate additional information to the interrupt handler.[1][2][3]
As an example, PCI Express does not have separate interrupt pins at all; instead, it uses special in-band messages to allow pin assertion or deassertion to be emulated. Some non-PCI architectures also use MSI; as another example, HP GSC devices do not have interrupt pins and can generate interrupts only by writing directly to the processor's interrupt register in memory space.[citation needed] The HyperTransport protocol also supports MSI.[4]
Advantages
[edit]While more complex to implement in a device, message signalled interrupts have some significant advantages over pin-based out-of-band interrupt signalling. On the mechanical side, fewer pins makes for a simpler, cheaper, and more reliable connector. While this is no advantage to the standard PCI connector, PCI Express takes advantage of these savings.
MSI increases the number of interrupts that are possible. While conventional PCI was limited to four interrupts per card (and, because they were shared among all cards, most are using only one), message signalled interrupts allow dozens of interrupts per card, when that is useful.[1]
There is also a slight performance advantage. In software, a pin-based interrupt could race with a posted write to memory. That is, the PCI device would write data to memory and then send an interrupt to indicate the DMA write was complete. However, a PCI bridge or memory controller might buffer the write in order to not interfere with some other memory use. The interrupt could arrive before the DMA write was complete, and the processor could read stale data from memory.[5] To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished. This read had a moderate performance penalty. An MSI write cannot pass a DMA write, so the race is eliminated.[6]
MSI types
[edit]PCI defines two optional extensions to support Message Signalled Interrupts, MSI and MSI-X. PCI Express defines its own message-based mechanism to emulate legacy PCI interrupts.
MSI
[edit]MSI (first defined in PCI 2.2) permits a device to allocate 1, 2, 4, 8, 16 or 32 interrupts. The device is programmed with an address to write to (this address is generally a control register in an interrupt controller), and a 16-bit data word to identify it. The interrupt number is added to the data word to identify the interrupt.[1] Some platforms such as Windows do not use all 32 interrupts but only use up to 16 interrupts.[7]
MSI-X
[edit]MSI-X (first defined in PCI 3.0) permits a device to allocate up to 2048 interrupts. The single address used by original MSI was found to be restrictive for some architectures. In particular, it made it difficult to target individual interrupts to different processors, which is helpful in some high-speed networking applications. MSI-X allows a larger number of interrupts and gives each one a separate target address and data word. Devices with MSI-X do not necessarily support 2048 interrupts.[3][8][9][10]
Optional features in MSI (64-bit addressing and interrupt masking) are also mandatory with MSI-X.
PCI Express legacy interrupt emulation
[edit]PCI Express does not have physical interrupt pins, but emulates the 4 physical interrupt pins of PCI via dedicated PCI Express Messages such as Assert_INTA and Deassert_INTC. Being message-based (at the PCI Express layer), this mechanism provides some, but not all, of the advantages of the PCI layer MSI mechanism: the 4 virtual pins per device are no longer shared on the bus (although PCI Express controllers may still combine legacy interrupts internally), and interrupt changes no longer inherently suffer from race conditions.
PCI Express permits devices to use these legacy interrupt messages, retaining software compatibility with PCI drivers, but they are required to also support MSI or MSI-X in the PCI layer.
x86 systems
[edit]On Intel systems, the LAPIC must be enabled for the PCI (and PCI Express) MSI/MSI-X to work, even on uniprocessor (single core) systems.[11][12] In these systems, MSIs are handled by writing the interrupt vector directly into the LAPIC of the processor/core that needs to service the interrupt. The Intel LAPICs of 2009 supported up to 224 MSI-based interrupts.[12] According to a 2009 Intel benchmark using Linux, using MSI reduced the latency of interrupts by a factor of almost three when compared to I/O APIC delivery.[13]
Operating system support
[edit]In the Microsoft family of operating systems, Windows Vista and later versions have support for both MSI and MSI-X. Support was added in the Longhorn development cycle around 2004.[14] MSI is not supported in earlier versions like Windows XP or Windows Server 2003.[15]
Solaris Express 6/05 released in 2005 added support for MSI an MSI-X as part of their new device driver interface (DDI) interrupt framework.[16]
FreeBSD 6.3 and 7.0 released in 2008 added support for MSI and MSI-X.[17]
OpenBSD 5.0 released in 2011 added support for MSI.[18] 6.0 added support for MSI-X.[19]
Linux gained support for MSI and MSI-X around 2003.[20] Linux kernel versions before 2.6.20 are known to have serious bugs and limitations in their implementation of MSI/MSI-X.[21]
Haiku gained support for MSI around 2010.[22] MSI-X support was added later, in 2013.[23]
NetBSD 8.0 released in 2018 added support for MSI and MSI-X.
VxWorks 7 supports MSI and MSI-X
See also
[edit]References
[edit]- ^ a b c d PCI Local Bus Specification Revision 2.2. PCI-SIG. December 1998.
{{cite book}}:|work=ignored (help) - ^ a b PCI Local Bus Specification Revision 2.3. PCI-SIG. 2002.
{{cite book}}:|work=ignored (help) - ^ a b c PCI Local Bus Specification Revision 3.0. PCI-SIG. August 2002.
{{cite book}}:|work=ignored (help) - ^ Don Anderson; Jay Trodden (2003). HyperTransport System Architecture. Addison-Wesley Professional. p. 200. ISBN 978-0-321-16845-0.
- ^ Coleman, James (2009). "Overview of Interrupt Delivery Methods, Legacy XT-PIC Interrupts, XT-PIC Limitations". Reducing Interrupt Latency Through the Use of Message Signalled Interrupts (PDF). Intel Corporation. p. 10.
- ^ Corbet, Jonathan; Rubini, Alessandro; Kroah-Hartman, Greg (2009). "Chapter 15: Memory Mapping and DMA". Linux Device Drivers (3rd ed.). O'Reilly Media. Retrieved 2019-04-20.
- ^ Microsoft. "Enabling Message-Signalled Interrupts in the Registry". Microsoft Corporation. Retrieved 12 April 2013.
- ^ "Section 6.1: MSI & MSI-X". PCI Express Base Specification Revision 1.0a. PCI-SIG. April 2003.
- ^ "Section 6.1: MSI & MSI-X". PCI Express Base Specification Revision 1.1. PCI-SIG. March 2005.
- ^ "MSI-X Engineering Change Notice". PCI Local Bus Specification Revision 2.3 (PDF). PCI-SIG.
- ^ APIC-Based Interrupt Subsystems on Uniprocessor PCs
- ^ a b Coleman, James (2009). Reducing Interrupt Latency Through the Use of Message Signalled Interrupts (PDF). Intel Corporation. pp. 10, 11.
- ^ Coleman, James (2009). "Results, Workstation Class Platform". Reducing Interrupt Latency Through the Use of Message Signalled Interrupts (PDF). Intel Corporation. p. 19.
- ^ Interrupt Architecture Enhancements in Microsoft Windows Vista, Aug 11, 2004
- ^ PCI, PCI-X, and PCI Express: Frequently Asked Questions, November 18, 2005, page 4
- ^ John Stearns, Govinda Tatti, Edward Gillett and Anish Gupta, (March 27, 2006) Changes made to support MSI in Solaris Express Advanced Interrupt Handlers in the Solaris Express 6/05 OS
- ^ John H. Baldwin, "PCI Interrupts for x86 Machines under FreeBSD", "availability" section
- ^ Mark Kettenis, (May 2011) MSI interrupts for many devices, on those architectures which can support them (amd64, i386, sparc64 only so far)
- ^ Mark Kettenis, (May 2016) Initial support for MSI-X has been added
- ^ MSI-HOWTO.txt first version
- ^ With Myri10GE, can I use MSI-X interrupts on Linux 2.6.18 and earlier?
- ^ [1] Haiku commit adding MSI support
- ^ [2] Haiku commit adding MSI-X support