Incisive Enterprise Specman® Elite Testbench (abbreviated simply as Specman) is a tool that automates certain steps of the semiconductor design and verification process and provides for functional coverage analysis at the architectural/specification level. It is part of the Cadence® Incisive® functional verification platform.
Specman is an EDA tool that provides advanced automated Functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the e Hardware Verification Language. Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification.
Introduction to Specman
The Specman Elite system provides three main enabling technologies intended to improve productivity:
- Constraint-driven test generation—Users control automatic test generation by capturing constraints from the interface specifications and the functional test plan.
- Data and temporal checking— Users create self-checking modules that ensure data correctness and temporal conformance. For data checking, reference model or rule-based approaches can be used.
- Functional coverage analysis— Users can measure the progress of verification efforts against a functional test plan.
The Specman tool itself does not include an HDL-simulation environment (such as VHDL or Verilog.) To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. In principle, Specman can co-simulate with any HDL-simulator supporting standard PLI or VHPI interface, such as Cadence's Incisive Enterprise Simulator (formerly known as NCSim), NC-Sim or Verilog-XL, Synopsys's VCS, or Mentor's Questa (formerly known as ModelSim)ModelSim, or Aldec's Riviera-PRO.
- Leverages the e language’s unique aspect-oriented programming capabilities
- “IntelliGen” constraint solvers automate test generation, and provide for distribution control and scalability
- Provides automatic data and assertion checking to speed debugging
- Captures executable specifications
- Increases predictability with functional coverage analysis
- Interfaces with all IEEE-standard languages including SystemC®, C++, VHDL, Verilog, and SystemVerilog. In addition, it directly supports e and C, and also interfaces with MATLAB.
- Supports built-in IP reuse to leverage existing investments in verification
- Works with all major simulators – the same testbench can be activated with different simulators, such as IES, VCS, Questa and OSCI. In addition, it also interfaces with Simulink.
e verification language and aspect-oriented programming support
Specman’s aspect-oriented e verification language can capture rules from executable specifications which can then be used and reused to automate verification. It enables or facilitates a number of other Specman features.
Constraint-driven stimulus generation
Specman provides “infinity-minus” constraint-driven test generation that automates the process of generating functional verification tests. By specifying constraints, engineers can target the generator to create any test in their functional test plan. They can also generate tests on-the-fly based on the current design state, making it possible to detect hard-to-reach corner cases. The “infinity-minus” methodology means that, by default, test generation is randomized (unless requested otherwise). This leads to very extensive state-space exploration, which in turn leads to finding corner case bugs.
Coverage driven distribution of constrained random stimuli
Specman’s coverage-driven-distribution rounds out the coverage provided by constraint driven generation. In coverage-driven-distribution, the random stimuli generator reads the functional coverage requirements, in addition to the constraint model, and derives the desired distribution to achieve them. The derived distribution complements the default distribution of the random generator and directs the generator toward “a better distribution” than the distribution that would be chosen from analyzing the constraint model alone.
Data and assertion checking
Specman’s temporal constructs allow verification specialists and designers to capture complex protocols for assertion checking. On-the-fly data checking and generation provides context-specific expected values. Verification engineers can use any combination of gray-, black-, or white-box checking to speed debugging.
HDL simulator interfaces
Specman integrates with all leading HDL simulators and supports a high-performance, direct kernel interface to the Incisive Enterprise Simulator. Users can sample and drive internal signals of the DUT. With 100% controllability and observability of otherwise inaccessible internal signals: all Specman engines have full access to signal values during simulation.
Transaction-level modeling and SystemC support
Specman provides SystemC interface mechanisms to drive and monitor transaction-level models (TLMs) as well as signal-level models. Users can apply Specman verification methodologies to the verification of SystemC architectural models using TLMs and reference models including mixed SystemC/RTL environments, and co-verify SystemC models used for software development. In addition Incisive simulator support, Specman provides interface adaptors for SystemC simulators including OSCI® and Synopsys ConvergenSC. Specman enables engineers to create a single verification environment to verify their SystemC model and then reuse it throughout the entire downstream flow, from RTL simulation to acceleration and emulation.
Specman supports all leading hardware/software co-verification tools, enabling seamless integration with Incisive Software Extensions to facilitate functional testing of both hardware and software. Early integration and debugging of HW/SW systems eliminates errors and shortens time to market for the combined system.
The Plan-to-Closure Methodology provides a system of best-known principles, guidelines, and procedures that span verification planning and management, assertion-based verification, testbench automation and reuse, and system-level verification. It includes documented best practices, golden examples that serve as templates to help engineers learn and apply the methodology, and libraries (code building blocks and utilities) that automate the process and eliminate many redundant verification-coding tasks, increase project productivity and predictability, and ensure overall system level quality. In addition, the Pl an-to-Closure “Knowledge System” (a web-based portal technology) allows users to research topics of interest, and then customize the methodology to their specific needs. Support for any testbench, HDL, software, or assertion IP Verification teams can extend the functionality of Specman technology to provide a high-throughput channel between the testbench and the device under test (DUT), and enable Plan-to-Closure verification automation of embedded software exactly as if it were another part of the DUT. With other elements from the Incisive platform, including verification IP, hardware acceleration and emulation, analog/mixed-signal/RF verification, and formal assertion verification, Specman products support any testbench, HDL, software, or assertion IP.
Support for any testbench, HDL, software, or assertion IP
Verification teams can extend the functionality of Specman technology to provide a high-throughput channel between the testbench and the device under test (DUT), and enable Plan-to-Closure verification automation of embedded software exactly as if it were another part of the DUT. With other elements from the Incisive platform, including verification IP, hardware acceleration and emulation, analog/mixed-signal/RF verification, and formal assertion verification, Specman products support any testbench, HDL, software, or assertion IP.
The Universal Verification Methodology (UVM) is the recognized, standardized methodology for verifying integrated circuit designs, and Specman is fully UVM-compliant. UVM is an Accellera standard developed with support from multiple vendors including Cadence. It is derived mainly from the OVM (Open Verification Methodology), which in turn was largely based on the older eRM (e Reuse Methodology) for the e verification language. Specman, the aspect-oriented e verification language, and eRM were all developed by Verisity, which was later acquired by Cadence.
It is now part of the Cadence's functional verification suite, "Incisive Enterprise Simulator", although Specman can still be licensed as a standalone product.
- History of Specman blog Blog Archive, a number of interesting links included at this Blog entry
- Interview Transcript, Interview: IEEE 1647-2008 standard update brings greater interoperability
- The e Hardware Verification Language, Sasan Iman and Sunita Joshi, Springer, May 28, 2004
- Aspect-Oriented Programming with the e Verification Language, David Robinson, 2007
- EDA Playground EDA Playground Site, Useful site for experimenting with verification languages including e / Specman
- Cadence Functional Verification web page Functional Verification Language Support, Landscape of verification languages and implementation standards including the e Verification Language IEEE 1647
- Cadence e HVL web page The e Hardware Verification Language in depth, Complete and concise information on differentiating features of the e Verification Language IEEE 1647, fully explained
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