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Synchronous circuit

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In digital electronics, a synchronous circuit is a digital circuit in which the changes in the state of memory elements are synchronized by a clock signal. In a sequential digital logic circuit, data is stored in memory devices called flip-flops or latches. The output of a flip-flop is constant until a pulse is applied to its "clock" input, upon which the input of the flip-flop is latched into its output. In a synchronous logic circuit, an electronic oscillator called the clock generates a string (sequence) of pulses, the "clock signal". This clock signal is applied to every storage element, so in an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. Ideally, the input to each storage element has reached its final value before the next clock occurs, so the behaviour of the whole circuit can be predicted exactly. Practically, some delay is required for each logical operation, resulting in a maximum speed limitations at which each synchronous system can run.

To make these circuits work correctly, a great deal of care is needed in the design of the clock distribution networks. Static timing analysis is often used to determine the maximum safe operating speed.

Nearly all digital circuits, and in particular nearly all CPUs, are fully synchronous circuits with a global clock. Exceptions are often compared to fully synchronous circuits. Exceptions include self-synchronous circuits,[1][2][3][4] globally asynchronous locally synchronous circuits, and fully asynchronous circuits.

See also[edit]


  1. ^ Asada and Ikeda Laboratories. "Self-synchronous Circuit". "Self Synchronous FPGA". 2009.
  2. ^ "self synchronous configurable logic blocks".
  3. ^ Devlin, Benjamin; Ikeda, Makoto; Asada, Kunihiro. "Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling". 2012. doi:10.1587/transele.E95.C.546
  4. ^ Devlin, B.; Ueki, H.; Mori, S.; Miyauchi, S.; Ikeda, M.; Asada, K. "Performance and side-channel attack analysis of a self synchronous montgomery multiplier processing element for RSA in 40nm CMOS". 2012. doi:10.1109/ASSCC.2012.6570807