System Management Mode
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|Microprocessor modes for the x86 architecture|
|First supported platform shown in parentheses|
System Management Mode (SMM, sometimes called ring -2 in reference to protection rings) is an operating mode of x86 central processor units (CPUs) in which all normal execution, including the operating system, is suspended. An alternate software system which usually resides in the computer's firmware, or a hardware-assisted debugger, is then executed with high privileges.
It was first released with the Intel 386SL. While initially special SL versions were required for SMM, Intel incorporated SMM in its mainline 486 and Pentium processors in 1993. AMD implemented Intel's SMM with the Am386 processors in 1991. It is available in all later microprocessors in the x86 architecture.
SMM is a special-purpose operating mode provided for handling system-wide functions like power management, system hardware control, or proprietary OEM designed code. It is intended for use only by system firmware, not by applications software or general-purpose systems software. The main benefit of SMM is that it offers a distinct and easily isolated processor environment that operates transparently to the operating system or executive and software applications.
In order to achieve transparency, SMM imposes certain rules. The SMM can only be entered through SMI (System Management Interrupt). The processor executes the SMM code in a separate address space that has to be made inaccessible to other operating modes of the CPU by the firmware.
Initially, System Management Mode was used for implementing Advanced Power Management (APM) features. However, over time, some BIOS manufacturers have relied on SMM for other functionality like making a USB keyboard work in real mode.
Some uses of the System Management Mode are:
- Handle system events like memory or chipset errors
- Manage system safety functions, such as shutdown on high CPU temperature and turning the fans on and off
- Security functions, such as flash device lock down require SMM support on some chipsets
- Deeper sleep power management support on Intel systems
- Control power management operations, such as managing the voltage regulator modules
- Emulate motherboard hardware that is unimplemented or buggy
- Emulate a PS/2 mouse and/or keyboard by converting the messages from USB versions of those peripherals to the messages that would have been generated had PS/2 versions of such hardware been connected (often referred to as USB legacy support)
- Centralize system configuration, such as on Toshiba and IBM notebook computers
- Emulate or forward calls to a Trusted Platform Module (TPM)
SMM is entered via the SMI (system management interrupt), which is caused by:
- Motherboard hardware or chipset signaling via a designated pin SMI# of the processor chip. This signal can be an independent event.
- Software SMI triggered by the system software via an I/O access to a location considered special by the motherboard logic (port 0B2h is common).
- An I/O write to a location which the firmware has requested that the processor chip act on.
By entering SMM, the processor looks for the first instruction at the address SMBASE (SMBASE register content) + 8000H (by default 38000H), using registers CS = 3000H and EIP = 8000H. The CS register value (3000H) is due to the use of real mode memory addresses by the processor when in SMM. In this case, the CS is internally appended with 0H on its rightmost end .
By design, the operating system cannot override or disable the SMI. Due to this fact, it is a target for malicious rootkits to reside in, including NSA's "implants" which have individual code names for specific hardware, like SOUFFLETROUGH for Juniper Networks firewalls, SCHOOLMONTANA for J-series routers of the same company, DEITYBOUNCE for DELL, or IRONCHEF for HP Proliant servers.
Improperly designed and insufficiently tested SMM BIOS code can make the wrong assumptions and not work properly when interrupting some other modes like PAE or 64-bit long mode. According to the documentation of the Linux kernel, around 2004, such buggy implementations of the USB legacy support feature were a common cause of crashes, for example on motherboards based on the Intel E7505 chipset.
Since the SMM code (SMI handler) is installed by the system firmware (BIOS), the OS and the SMM code may have expectations about hardware settings that are incompatible, such as different ideas of how the Advanced Programmable Interrupt Controller (APIC) should be set up.
Operations in SMM take CPU time away from the applications, operating system kernel and hypervisor, with the effects magnified for multicore processors since each SMI causes all cores to switch modes. There is also some overhead involved with switching in and out of SMM, since the CPU state must be stored to memory (SMRAM) and any write-back caches must be flushed. This can destroy real-time behavior and cause clock ticks to get lost. The Windows and Linux kernels define an ‘SMI Timeout’ setting a period within which SMM handlers must return control to the operating system or it will ‘hang’ or ‘crash’.
The SMM may disrupt the behavior of real-time applications with constrained timing requirements.
A digital logic analyzer may be required to determine if the CPU has entered SMM (checking state of SMIACT# pin of CPU). Recovering the SMI handler code to analyze it for bugs, vulnerabilities and secrets requires a logic analyzer or disassembly of the system firmware.
- Coreboot – includes an open source SMM/SMI handler implementation, for some chipsets
- Intel 80486SL
- MediaGX – a processor which emulates nonexistent hardware via SMM
- Ring -3
- Unified Extensible Firmware Interface (UEFI)
- Domas, Christopher (20 July 2015). "The Memory Sinkhole" (PDF). Black Hat. Retrieved 22 August 2015.
- Tereshkin, Alexander and Wojtczuk, Rafal (29 July 2009). "Introducing Ring -3 Rootkits" (PDF). Invisible Things Lab, Black Hat USA. p. 4. Retrieved 22 August 2015.
- "SMIs Are EEEEVIL (Part 1)". msdn.com. Microsoft.
- "AMD Am386®SX/SXL/SXLV Datasheet" (PDF). AMD.
- "Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 3B" (PDF). Intel.
- "SMIs Are EEEEVIL (Part 2)". msdn.com. Microsoft.
- Vojtech Pavlik (January 2004). "Linux kernel documentation: USB Legacy support". kernel.org. Retrieved 2013-10-06.
- Google Tech Talks - Coreboot - 00:34:30
- Robert McMillan (10 May 2008). "Hackers find a new place to hide rootkits". InfoWorld.
- Rob Williams (7 August 2015). "Researchers Discover Rootkit Exploit In Intel Processors That Dates Back To 1997". HotHardware.com.
- Intel's System Management Mode by Robert R. Collins
- US 5963738 - Computer system for reading/writing system configuration using I/O instruction
- Loïc Duflot. "Security Issues Related to Pentium System Management Mode" (PDF). Retrieved 2013-10-06.
- Shawn Embleton; Sherri Sparks; Cliff Zou (September 2008). "SMM Rootkits: A New Breed of OS Independent Malware" (PDF). ACM. Retrieved 2013-10-06.
- "Hackers Find a New Place to Hide Rootkits". PC World. 2008-05-09. Retrieved 2013-10-06.
- #1 Source for Leaks Around the World! (2013-12-30). "NSA's ANT Division Catalog of Exploits for Nearly Every Major Software/Hardware/Firmware | LeakSource". Leaksource.wordpress.com. Retrieved 2014-01-13.
- January 13, 2014 at 2:45 PM • 2 Comments (2013-12-30). "Schneier on Security: SOUFFLETROUGH: NSA Exploit of the Day". Schneier.com. Retrieved 2014-01-13.
- January 15, 2014 at 2:56 PM • 6 Comments (2008-05-30). "Schneier on Security: SCHOOLMONTANA: NSA Exploit of the Day". Schneier.com. Retrieved 2014-01-16.
- "Schneier on Security". schneier.com.
- "Schneier on Security: IRONCHEF: NSA Exploit of the Day". Schneier.com. January 3, 2014. Retrieved 2014-01-13.
- Brian Delgado and Karen L. Karavanic, "Performance Implications of System Management Mode," 2013 IEEE International Symposium on Workload Characterization, Sept. 22-24, Portland, OR USA.
- AMD Hammer BIOS and Kernel Developer's guide, Chapter 6 (archived from the original on December 7, 2008)
- Intel 64 and IA-32 Architectures Developer's Manual, Volume 3C, Chapter 34