Talk:AMD K6-III

	This article is within the scope of WikiProject Computing, a collaborative effort to improve the coverage of computers, computing, and information technology on Wikipedia. If you would like to participate, please visit the project page, where you can join the discussion and see a list of open tasks.ComputingWikipedia:WikiProject ComputingTemplate:WikiProject ComputingComputing articles
???	This article has not yet received a rating on the project's importance scale.
	This article is supported by Computer hardware task force.

The end of the paragraph with this text:

"The K6-III, however, used both methods: it had 64 KiB primary cache, a massive 256 KiB on-chip, full-speed secondary cache (similar to the Celeron's but twice the size), and the variable size motherboard mounted cache on the Socket 7 main board became a tertiary level."

is confusing. It implies four levels of cache, which I don't think is accurate. Specifically I thought "on-chip" and "primary" caches were the same thing. Can anyone who knows please clarify the article? Thanks!

71.145.192.67 23:22, 27 January 2006 (UTC)[reply]

Primary cache = L1 Cache, econdary = L2-Casche, tertiary = L3-Cache, where's the fourth one ? --Denniss 01:02, 28 January 2006 (UTC)[reply]

I see. I had misread the original statement. I thought "a massive 256 KiB on-chip, full-speed secondary cache (similar to the Celeron's but twice the size)" was talking about two different caches, but I see the comma is just there to separate the adjectives. I'm not sure it would be better without the comma. Thanks for the clarification. --71.145.203.147 15:58, 30 January 2006 (UTC)[reply]

K6+ chips were lucky to hit 600 MHz, especially the III+. I personally have had 2 of them, neither of which could do 600 MHz regardless of how cool I kept them or how much voltage they received. Seems to be similar to what others have seen, from the overclocking databases around the web. K6 core has a very short 6 stage pipeline (a lot shorter than even P3) which prevents high clocks (see the 31 stage P4 Prescott!). --Swaaye 02:31, 8 April 2006 (UTC)[reply]

A lot of people at K6Plus.com reached 600 MHz with these chips and still run them today. A lot of it was simply the luck of the draw; some of them needed 2.1 or 2.2v to get there. Some of them could hit 600 on as little as 1.8v. And some won't do it at all--my K6-III+ 450 can do 550 on 1.9, but won't make 600 even on 2.3. The record overclock, AFAIK, is 744 MHz (124*6) for a K6-III+ 550 (yes, they exist) on an FIC VA-503+. Incidentally, these chips with their L3 caches are still very capable for anything not FPU-intensive. Jsc1973 (talk) 03:32, 12 February 2009 (UTC)[reply]

Fair use rationale for Image:TmpphpqbEbau.png

Image:TmpphpqbEbau.png is being used on this article. I notice the image page specifies that the image is being used under fair use but there is no explanation or rationale as to why its use in this Wikipedia article constitutes fair use. In addition to the boilerplate fair use template, you must also write out on the image description page a specific explanation or rationale for why using this image in each article is consistent with fair use.

Please go to the image description page and edit it to include a fair use rationale. Using one of the templates at Wikipedia:Fair use rationale guideline is an easy way to insure that your image is in compliance with Wikipedia policy, but remember that you must complete the template. Do not simply insert a blank template on an image page.

If there is other fair use media, consider checking that you have specified the fair use rationale on the other images used on this page. Note that any fair use images uploaded after 4 May, 2006, and lacking such an explanation will be deleted one week after they have been uploaded, as described on criteria for speedy deletion. If you have any questions please ask them at the Media copyright questions page. Thank you.

BetacommandBot 22:03, 25 October 2007 (UTC)[reply]