Talk:AND gate

From Wikipedia, the free encyclopedia
Jump to: navigation, search
WikiProject Electronics (Rated Start-class, Mid-importance)
WikiProject icon This article is part of WikiProject Electronics, an attempt to provide a standard approach to writing articles about electronics on Wikipedia. If you would like to participate, you can choose to edit the article attached to this page, or visit the project page, where you can join the project and see a list of open tasks. Leave messages at the project talk page
Start-Class article Start  This article has been rated as Start-Class on the project's quality scale.
 Mid  This article has been rated as Mid-importance on the project's importance scale.
 

Alternatives[edit]

The bottom "alternatives" section could show that NOR gates (not only NAND gates) can be used to create the equivalent of an AND gate. NAND and NOR gates are called the "universal gates" because they can be used to create any other gate: AND, OR, NOT. Is there an official way to create schematics? I have Xilinx available because it's free from their website, but my schematics would appear differently from the ones currently shown. ~Kruck 02:14, 27 October 2006 (UTC)

Done. — Preceding unsigned comment added by Roshan220195 (talkcontribs) 14:07, 4 April 2012 (UTC)

Picture is wrong.[edit]

Picute for PCOS AND gate implementatino is wrong —The preceding unsigned comment was added by 216.31.219.19 (talk) 01:58, 5 December 2006 (UTC).

True story. The p-mos transistors need to be in parallel in order to function analogously to the n-mos transistors in series. bdieseldorff 18:56, 15 September 2007 (UTC)

I agree too, the one in the diagram is of an or. —Preceding unsigned comment added by 190.128.84.48 (talk) 00:33, 30 September 2008 (UTC)

Agreed, removed. --Paul Vernaza (talk) 02:24, 13 December 2008 (UTC)

mentioning Philips[edit]

Is it needed to mention Philips as a semiconductor manufacturer, I think this seems like an advertising for the brand. --Carlos.javierloy 01:29, 4 June 2007 (UTC) Carlos J. Loya

The physical layout[edit]

Would it be helpful to add a diagram for the physical layout of a CMOS AND. We have it for NAND.--Ademkader (talk) 15:05, 19 November 2007 (UTC)

Alternate notation[edit]

AND gates in circuit complexity use the ^ notation (upside down V) —Preceding unsigned comment added by 71.232.103.200 (talk) 02:31, 15 May 2008 (UTC)

Would be helpful to include a diagram of AND gate constructed using only NAND gates

Clearer Equation[edit]

I think there should be a clearer equation for the AND gate like the one XOR Output=[Input1+Input2]/Max Melab-1 (talk) 18:14, 21 August 2008 (UTC)

Implementation[edit]

The AND gate can also be implemented using diodes. Is it ok to mention that? Roshan220195 (talk) 16:55, 25 March 2012 (UTC)