Talk:Standard cell

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The original article seemed to emphasize the development of standard-cell libraries. I changed the article to reflect the much greater (industry) activity in use/application of standard-cell based ASIC design.

Proposed merge from Library (electronics)

I think these articles are sufficiently related that I would merge the library article (as the less complete one) into this article. RupertMillard (Talk) 17:39, 14 October 2007 (UTC)[reply]

Agreed. Furthermore I would suggest renaming "Library" to "Standard Cell Library".Nelziq (talk) 23:21, 18 December 2007 (UTC)[reply]

I think it would be best to merge these two, as long as the Standard Cell Library had its own section and it was defined —Preceding unsigned comment added by 207.218.136.73 (talk) 15:21, 10 September 2008 (UTC)[reply]

Gate

What's meant with gate as used in this article? Is it synonymous to standard cell? Or is it, regarding abstraction, something between a transistor and a standard cell? Thanks, --Abdull (talk) 18:49, 24 June 2008 (UTC)[reply]

In this article, "gate" means logic gate -- an abstract Boolean function. For example, anything with 3 inputs and one output, which has a high output when all three inputs are low and a low output otherwise, is a "3-input NOR gate". A gate is not exactly synonymous with a standard cell. A "3-input NOR gate standard cell" is one of many possible implementations of that abstract "NOR gate" function; a "3-input NOR resistor–transistor logic gate" is another implementation. A standard cell library typically includes implementations of all the common gates, the so-called "three-state logic buffer", and also includes a few "cells" that implement more complex multi-logic-gate functions such as flip-flops. (Are those more complex cells called macrocells ?)

There is one confusing exception -- the sentence that begins "The reddish structures are polysilicon gates" refers to a different kind of gate, the "gate terminal" of a MOSFET. Some implementations of a logic gate, such as a 3-input NOR gate, don't use any such "gate terminals"; other implementations of a 3-input NOR gate may have 3 or 6 "gate terminals".

How can we make this article less confusing? --DavidCary (talk) 23:44, 13 June 2013 (UTC)[reply]

LVS

LVS does not necessarily merge transistors. I think it depends on the rules, but certain kits provide rules where even the fingering is checked as opposed to the total width only (if I'm reading correctly what was written). However, I do not think that this example is necessary, to be honest. More interesting would be pointers to some algorithms for LVS, if someone decides to take up on writing a proper LVS tool since every and each one of them I had a misfortune to be using was, plainly put, almost useless and pretty poorly written ... hard, deep stare is very often more useful than LVS ... —Preceding unsigned comment added by 18.62.30.17 (talk) 16:41, 21 July 2009 (UTC)[reply]