Template talk:Multimedia extensions

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remove SSE5?[edit]

The SSE5 instruction set was proposed by AMD, but they changed it to XOP for the sake of compatibility with AVX. SSE5 has thus never been implemented and never will. Should SSE5 be removed from the list? Afog (talk) 08:00, 8 June 2009 (UTC)

Separate list for AMD-only instructions?[edit]

3DNow, XOP and CVT16 are/will be implemented only in AMD processors. The rest are/will be implemented in both Intel, AMD and possibly other processors. It is uncertain whether FMA4 will be supported by Intel. It is possible that part of XOP will be supported by Intel in the future if it becomes popular. Should the list reflect which instruction sets are for AMD only, or will that make the template too big and confusing? Afog (talk) 08:00, 8 June 2009 (UTC)

I think 3DNow! was also implemented by Cyrix, IDT, and VIA. I don't really mind how the x86 instruction sets are organized. Rilak (talk) 13:17, 9 June 2009 (UTC)

Is it me or is the text for 3dNow a bit screwed up? Andrewhime (talk) 08:25, 12 April 2011 (UTC)

Can we separate instruction set nomenclature by colour coded between Intel, AMD and both? Rjluna2 (talk) 20:39, 19 June 2015 (UTC)

delete and recreate[edit]

I would delete this article and create a new one named "Instruction set Extensions"; there I would include all available Extensions to the known Instruction sets, especially AES-NI, Transactional_Synchronization_Extensions, VT-d, VT-x, Marvell CESA, Via Padlock, EIST, etc. Semsi Paco Virchow (talk) 07:00, 5 July 2013 (UTC)

instructions in x86 versus instructions in extensions[edit]

Can anybody tell me, where I find a comparison of the existent instructions in x86 versus all the ones added by extensions? Semsi Paco Virchow (talk) 07:01, 5 July 2013 (UTC)

RISC formatting[edit]

I don't really like the PA-RISC (MAX) format; it seems like MAX (PA-RISC) would make more sense. Do any wiki formatting wizards know how to make that change? Do people agree with it? Risc64 (talk) 16:25, 4 June 2016 (UTC)