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A ceramic capacitor is a fixed value capacitor with the ceramic material acting as the dielectric. It is constructed of two or more alternating layers of ceramic and a metal layer acting as the electrodes. The composition of the ceramic material defines the electrical behavior and therefore the application of the capacitors, which are divided into two stability classes:
- Class 1 ceramic capacitors with high stability and low losses for resonant circuit application.
- Class 2 ceramic capacitors with high volumetric efficiency for buffer, by-pass and coupling applications.
Ceramic capacitors, especially the multilayer version (MLCC), are the most produced and used capacitors in electronic equipment with a produced quantity of approximately 1000 billion pieces per year.
Ceramic capacitors of special shapes and styles are used as capacitors for RFI/EMI suppression, as feed-through capacitors, and in larger dimensions as power capacitors for transmitters.
Since the beginning of the study of electricity, ceramics like porcelain have been used as insulators. It was obvious to use these ceramic materials, including mica, steatite and titanium dioxide (rutile), as dielectric for the first ceramic capacitors. The capacitors with paraelectric titanium dioxide as a dielectric had a linear temperature dependence of the capacitance for temperature compensation of resonant circuits and were produced in small quantities around 1926. But this dielectric had relatively low permittivity so that only smaller capacitance values could be realized.
After 1941, the ferroelectric ceramic material barium titanate, with a permittivity in the range of 1000, approximately 10 times higher than titanium dioxide, was also used. The higher permittivity resulted in much higher capacitance values, but this was coupled with some unstable electrical parameters. At that time, these ceramic capacitors replaced the commonly used mica capacitors for a lot of applications where stability was not so important. Smaller dimensions, as compared to the mica capacitors, cheaper production costs and independence from natural mica product accelerated the development of these new ceramic capacitors.
The fast-growing broadcasting technology after the Second World War brought a great deepening of knowledge in understanding the crystallography, phase transitions, and the chemical and mechanical optimization of the ceramic materials. Through the complex mixture of different basic materials, the electrical properties of ceramic capacitors can be precisely adjusted. To distinguish the electrical properties of ceramic capacitors, standardization created application classes. Class 1 capacitors with paraelectric dielectric includes capacitors with a defined temperature coefficient for temperature compensation of circuits requiring high frequency accuracy. Class 2 capacitors with ferroelectric dielectric have higher capacitance values and include ceramic capacitors for decoupling, buffering and filtering in power supplies.
The typical shape of the capacitors for radio applications at this time was the ceramic tubular condenser. This was a ceramic tube that was covered with tin or silver on both the inside and outside surface, and was provided with relatively long lead terminals forming, together with resistors and other components, a typical wired tangle of open circuit wiring.
The easy formability of the ceramic material facilitated the development of some special and quite large shapes of ceramic capacitors for high-voltage, high-frequency (RF) and power applications.
With the development of semiconductor technology in the 1950s, barrier layer capacitors, or class 3 capacitors, were developed using doped ferroelectric ceramics. Because the electrical parameters of these capacitors were exceedingly temperature dependent, they would be replaced some decades later by Y5V class 2 capacitors.
In addition to the typical early ceramic tubular capacitor, the more inexpensively produced ceramic disc capacitors were introduced into the industry in the 1950s and 1960s.
It was a U.S. company in the midst of the Apollo program, which was launched in 1961, that first came up with the idea of stacking multiple discs to a monolithic block. This “multi-layer ceramic capacitor” (MLCC) was invented to meet the need for a compact, high-capacitance capacitor. The production of these capacitors using the tape casting and ceramic-electrode cofiring processes meant a great challenge in precision and technology. MLCCs expanded the range of ceramic capacitor application to larger capacitance values in smaller cases. These ceramic chip capacitors were the driving force behind the conversion of the production of electronic devices from through-hole mounting to surface-mount technology in the 1980s.
As of 2012[update], more than 1012 MLCC were manufactured each year. They are the most produced capacitors ever. Along with ceramic chip capacitors, ceramic disc capacitors are often used as so called safety capacitors in EMI suppression applications. Besides these, large ceramic power capacitors for high voltage or high frequency transmitter applications are also to be found.
New developments in ceramic materials have been made with anti-ferroelectric ceramics. This material has a nonlinear antiferroelectric/ferroelectric phase change, which allows greatly increased energy storage with higher volumetric efficiency. They are used for energy storage (for example, in detonators).
Application classes for ceramic capacitors 
Classes, disambiguation 
Several standards define and specify so-called “application classes” or short “classes” for the different characteristics of ceramic capacitors. These characteristics are based on the different materials used for the capacitors. Very stable and linear behavior of capacitance values within a specified temperature range and low losses at high frequencies are the result of using mixtures of paraelectric substances based on titanium dioxide. But these mixtures have a relatively low permittivity so that the capacitance values of these capacitors are relatively small.
Higher capacitance values for ceramic capacitors can be attained by using mixtures of ferroelectric materials like barium titanate together with specific oxides. These dielectric materials have much higher permittivities, but at the same time their capacitance value are more or less nonlinear over the temperature range, and losses at high frequencies are much higher.
These different materials are the reason for the division of ceramic capacitors into different classes. Regarding international standardization, the IEC (including the European standards EN) specify two application classes:
- Class 1 ceramic capacitors with high stability and low losses for resonant circuit application
- Class 2 ceramic capacitors with high volumetric efficiency for decoupling, smoothing, by-pass and coupling applications
In addition to these two classes, the IEC standard had specified in the 1960/1970s a third class:
- Class 3 barrier layer capacitors or semiconductive ceramic capacitors. These capacitors have a very high permittivity but much lower stability of the capacitance value than class 2 capacitors. Because it is not possible to build multilayer capacitors with this doped ferroelectric ceramic material, the production of this capacitor today (2012) is only run in very small quantities for leaded single layer types. The “class 3” ceramic capacitor is no longer defined in the IEC standard.
In the past, ceramic capacitors were not limited to specification by an IEC standard. Manufacturers, especially in the US, preferred EIA standards. In many parts very similar to the IEC standard, the EIA RS-198 defines four application classes for ceramic capacitors.
- Class I or also written class 1 ceramic capacitors with high stability and low losses for resonant circuit application
- Class II or class 2 ceramic capacitors with high volumetric efficiency for buffer, by-pass and coupling applications
- Class III or class 3 ceramic capacitors with higher volumetric efficiency than class II and typical change of capacitance by -22% to +56% over a temperature range of 10 °C to 55 °C. They are comparable with class 2- Y5T/Y5U/Y5V capacitors of IEC definition
- Class IV or class 4 are barrier layer capacitors
The different class numbers within both standards are the reason for a lot of misunderstandings interpreting the class descriptions in the datasheets of many manufacturers. The EIA ceased operations on February 11, 2011, but the former sectors continue to serve international standardization organizations. In the following, the definitions of the IEC standard will be preferred and in important cases compared with the definitions of the EIA standard.
Class 1 ceramic capacitors 
Class 1 ceramic capacitors are accurate, temperature-compensating capacitors. They are the most stable over voltage, temperature, and to some extent, frequency. They also have the lowest losses and therefore they are especially suited for resonant circuit application where these characteristics are essential or where a precisely defined temperature coefficient is required, for example in compensating temperature effects for a circuit.
The basic materials of class 1 ceramic capacitors are composed of a mixture of finely ground granules of paraelectric materials such as Titanium dioxide (TiO2), modified by additives of Zn, Zr, Nb, Mg, Ta, Co and Sr, which are necessary to achieve the capacitor’s desired linear characteristics.
Class 1 ceramic capacitors have the lowest volumetric efficiency of the different types of ceramic capacitors. This is the result of the relatively low permittivity (6 to 200) of the paraelectric ceramic materials. Therefore, the class 1 capacitors have capacitance values in the lower values range.
The temperature behavior of the capacitance of class 1 capacitors depends on the basic ferroelectric material, for example Titanium dioxide (TiO2), together with the composition of the different chemical additives. The chemical composition can be adjusted precisely so that the temperature characteristic of the capacitors can be determined by given targets.
A class 1 capacitor will have a temperature coefficient that is typically fairly linear with temperature. These capacitors have very low electrical losses with a dissipation factor of approximately 0.15%. They have no significant aging processes and the capacitance value is nearly independent from the voltage applied. These all allow applications for high Q filters, in resonant circuits and oscillators (for example, in phase-locked loop circuits).
Referring to the EIA RS-198 standard, ceramic class 1 capacitors will be coded with a three character code that indicates temperature coefficient. Here, the first letter gives the significant figure of the change in capacitance over temperature (temperature coefficient α) in ppm/K. The second character gives the multiplier of the temperature coefficient. The third letter gives the maximum tolerance from that in ppm/K. All ratings are from 25 to 85 °C:
|Temperature coefficient α
of the temperature coefficient
of the temperature coefficient
|C: 0.0||0: -1||G: ±30|
|B: 0.3||1: -10||H: ±60|
|L: 0.8||2: -100||J: ±120|
|A: 0.9||3: -1000||K: ±250|
|M: 1.0||4: +1||L: ±500|
|P: 1.5||6: +10||M: ±1000|
|R: 2.2||7: +100||N: ±2500|
|S: 3.3||8: +1000|
In addition to the EIA code, the temperature coefficient of the capacitance dependence of class 1 ceramic capacitors is commonly expressed in ceramic names like “NP0”, "N220" etc. These names correlate with the temperature coefficient (α) of the ceramic material. Referring to the standards IEC/EN 60384-8/21, this temperature coefficient and the tolerance of it will be replaced by a two digit letter code (see table) in which the corresponding EIA code is added.
For instance, an “NP0” capacitor with the EIA code “C0G” will have 0 drift, with a tolerance of ±30 ppm/K, while an "N1500" with the code "P3K" will have −1500 ppm/K drift, with a maximum tolerance of ±250 ppm/°C. Note that the IEC and EIA capacitor codes are industry capacitor codes and not military capacitor codes.
As the table shows, class 1 ceramic capacitors can be produced in many different temperature coefficients α of the capacitance. Especially, the material “NP0” or “CG” (IEC) “C0G” (EIA) with an α ±0•10−6 /K and an α tolerance of 30 ppm is technically of great interest. These capacitors have a capacitance aberration dC/C of ±0.54% within the total temperature range of -55 to +125 °C. This is a perfect base for a very accurate frequency response over a wide temperature range (in, for example, resonant circuits). The other materials with their special temperature behavior are used to compensate a counter temperature run of parallel connected components like coils in oscillator circuits. Class 1 ceramic capacitors are supplied with very small tolerances of the rated capacitance (see capacitance values and tolerances).
Class 2 ceramic capacitors 
Class 2 ceramic capacitors are capacitors that have a dielectric with a high permittivity and therefore a better volumetric efficiency than class 1 capacitors, but lower accuracy and stability. The ceramic dielectric is characterized by a nonlinear change of capacitance over the total temperature range. The capacitance value, additionally, depends on the voltage applied. They are suitable for by-pass and coupling applications or for frequency discriminating circuits where low losses and high stability of capacitance are not of major importance.
Class 2 ceramic capacitors are made of ferroelectric materials such as barium titanate (BaTiO3) and suitable additives such as aluminium silicate, magnesium silicate and aluminium oxide. These ceramics have a high, up to very high permittivity (200 to 14,000), which depends on the field strength applied. Hence the capacitance value of class 2 capacitors is nonlinear. It depends on temperature and voltage applied. Additionally, class 2 capacitors age over time.
However, the high permittivity allows production of high capacitance values in small dimensions. Class 2 capacitors are significantly smaller than class 1 capacitors at the same rated capacitance and voltage. They are suitable for applications that require the capacitor to maintain only a minimum value of capacitance, for example, buffering and filtering in power supplies as well as coupling and decoupling of electric signals.
Class 2 ceramic capacitors are divided into categories that give information about the change in capacitance over the temperature range. The most widely used classification is based on the EIA RS-198 standard and specifies a three-digit code. The first character is a letter that gives the low-end operating temperature. The second gives the high-end operating temperature, and the final character gives capacitance change over that temperature range:
change of capacitance
over the temperature range
|X = −55 °C (−67 °F)||4 = +65 °C (+149 °F)||P = ±10%|
|Y = −30 °C (−22 °F)||5 = +85 °C (+185 °F)||R = ±15%|
|Z = +10 °C (+50 °F)||6 = +105 °C (+221 °F)||S = ±22%|
|7 = +125 °C (+257 °F)||T = +22/−33%|
|8 = +150 °C (+302 °F)||U = +22/−56%|
|V = +22/−82%|
For instance, a Z5U capacitor will operate from +10 °C to +85 °C with a capacitance change of at most +22% to −56%. An X7R capacitor will operate from −55 °C to +125 °C with a capacitance change of at most ±15%.
Some commonly used class 2 ceramic capacitor materials are listed below:
- X7R (−55/+125 °C, ΔC/C0 = ±15%),
- Z5U (+10/+85 °C, ΔC/C0 = +22/−56%)
- Y5V (−30/+85 °C, ΔC/C0 = +22/−82%)
- X7S (−55/+125, ΔC/C0 = ±22%) and
- X8R (−55/+150, ΔC/C0 = ±15%).
As well as the commonly used EIA codes for the different class 2 ceramic materials, the international IEC standardization specifies, with the standards IEC/EN 60384 -9/22, another two-digit-code.
|Code for capacitance change||Max. capacitance change
ΔC/C0 at U = 0
|Max. capacitance change
ΔC/C0 at U = UN
|Code for temperature range||Temperature range|
|2B||±10%||+10/−15%||1||−55 … +125 °C|
|2C||±20%||+20/−30%||2||−55 … +85 °C|
|2D||+20/−30%||+20/−40%||3||−40 … +85 °C|
|2E||+22/−56%||+22/−70%||4||−25 … +85 °C|
|2F||+30/−80%||+30/−90%||5||(-10 … +70) °C|
|2R||±15%||−||6||+10 … +85 °C|
In most cases it is possible to decode the class 2 ceramic EIA code into the IEC/EN code. Small differences commonly found, normally are tolerable.
- X7R correlates with 2X1
- Z5U correlates with 2E6
- Y5V similar to 2F4, aberration: ΔC/C0 = +30/−80% instead of +30/−82%
- X7S similar to 2C1, aberration: ΔC/C0 = ±20% instead of ±22%
- X8R no IEC/EN code available
Because class 2 ceramic capacitors have a lower capacitance accuracy and stability, they are supplied in larger tolerances than class 1 capacitors, see chapter “Capacitor values and tolerances”.
For military types the Class 2 dielectrics are specified for temperature characteristic (TC) but not temperature-voltage characteristic (TVC). Similar to X7R, military type BX cannot vary more than 15 % over temperature, but in addition, it must remain within +15 %/-25 % at maximum rated voltage. Type BR has a TVC limit of +15 %/-40 :%.
Class 3 ceramic capacitors 
Class 3 barrier layer or semiconductive ceramic capacitors are capacitors that have a dielectric with a very high permittivity up to 50,000 and therefore a better volumetric efficiency than class 2 capacitors. These capacitors have worse electrical characteristics than Class 2, lower accuracy and stability. The ceramic dielectric is characterized by a very high nonlinear change of capacitance over the total temperature range. The capacitance value additionally depends on the voltage applied. As well, they have very high losses and age over time.
Barrier layer ceramic capacitors are made of doped ferroelectric materials such as barium titanate (BaTiO3). As this ceramic technology has improved in the mid of 1980, barrier layer capacitors are available in values of up to 100 µF, and they are increasingly starting to compete with electrolytic capacitors.
Barrier layer capacitors are now rather rare and considered obsolete, as modern multilayer ceramics can offer better performance in a compact package. As a consequence, the “class 3” ceramic capacitors are no longer defined in the actual IEC standard.
Construction and styles 
Ceramic capacitors are composed of a mixture of finely ground granules of paraelectric or ferroelectric materials, modified by a lot of accurate mixes, which are necessary to achieve the capacitor’s desired characteristics, see chapter "Application classes for ceramic capacitors". From these powder mixtures, the ceramic of the capacitor is sintered at high temperatures. The ceramic forms the dielectric of the capacitor and serves as a carrier of the metallic electrodes. The minimum thickness of the dielectric layer, which today (2012) is in the size range of 1 micron or smaller, is limited downwards by the grain size of the ceramic powder. Upwards, the thickness of the ceramic dielectric is determined by the dielectric strength of the desired capacitor. On the ceramic layer, the electrodes of the capacitor are deposited by metallization. For multilayer ceramic capacitors, alternating metallized ceramic layers, as many as necessary, are stacked one above the other. The outstanding metallization of the electrodes at two sides of the body are then contacted with the contacting terminal. A lacquer or ceramic coating protects the capacitor against ambient influences like moisture.
Ceramic capacitors come in various shapes and styles. Some of the most commonly used styles are:
- Multilayer ceramic chip capacitor (MLCC), rectangular block, for surface mounting
- Ceramic disc capacitor, single layer disc, resin coated, with through-hole leads
- Feedthrough ceramic capacitor, with a defined value of capacitance, which is used for bypass purposes in high-frequency circuits. Tube shape, inner metallization contacted with a lead, outer metallization for soldering
- Ceramic power capacitors, larger ceramic bodies in different shapes for high voltage applications
Multi-layer ceramic capacitors (MLCC chips) 
Ceramic capacitors, especially the multi-layer version (MLCC), are the most highly produced and most commonly used capacitors in electronic equipment. For this reason they earn special attention.
Manufacturing process 
A ceramic multilayer chip capacitor consists of a number of individual ceramic capacitors that are stacked together in parallel and contacted via the terminal surfaces. Starting material for all MLCC chips is a mixture of finely ground granules of paraelectric or ferroelectric raw materials, modified by accurately determined additives. Out of these basic materials a powder will be produced. The composition of the powder mixture and the size of the powder particles, which now goes down to the size range of 10 nm, represent the knowledge and the expertise of the capacitor manufacturer. These materials are mixed together homogeneously. A thin ceramic foil is cast from the suspension of ceramic powder with a suitable binder. This foil will first be rolled up for further transport. Unrolled again, it is cut into equal-sized sheets, which are printed with a metal paste by screen printing. These sheets are the future electrodes. In an automated process, these sheets are stacked in, for the particular capacitor, the required number of layers and solidified by pressing. Besides the relative permittivity of the ceramic, the size and the number of layers determines the later capacitance value of the capacitor. Taken into consideration during the stacking is, that the electrodes are stacked in an alternating arrangement slightly offset to each other so that they each can later be contacted like a comb, one-sided with the connecting terminals. The layered stack is pressed and then cut into individual capacitors. Here they get their future size. High mechanical precision is required, for example, to stack size "0201" (0.5 mm × 0.3 mm) with 500 or more printed layers. After cutting, first the binder is burnt out of the stack. This is followed by the sintering process. Here the ceramic powder will be sintered at temperatures between 1200 and 1450 °C and the ceramic receives its final, mainly crystalline, structure. Through this burning process the capacitors receive their desired dielectric properties. The burning process is followed by a cleaning and then the outer metallization of both end surfaces. Through the metallization, the end surfaces of the ceramic stack and the inner electrodes are connected in parallel and the capacitor gets its terminals. After completion of this manufacturing process follows a complete final inspection of the electrical values and the taping of the capacitors for automated processing in a manufacturing device.
The formula for capacitance (C) of a MLCC capacitor is based on the formula for a plate capacitor enhanced with the number of layers:
(ε stands for dielectric permittivity; A for electrode surface area; n for the number of layers; and d for the distance between the electrodes).
According to the equation, a thinner dielectric or a larger electrode area both will increase the capacitance value, as will a dielectric material of higher permittivity. With the progressive miniaturization of digital electronics in recent decades, the components on the periphery of the integrated logic circuits have to get smaller as well. Especially for the needed MLCC chips used around the microprocessors, the requirements for minimizing are very hard. To minimize a multi-layer chip capacitor, first, the thickness of the dielectric can be reduced and, second, the number of layers can be increased. Both options require huge efforts and are connected with a lot of expertise.
The development in miniaturizing is shown in the picture below. In 1995 the minimum thickness of the dielectric was 4 microns, in 2005 some manufacturers could even produce MLCC chips with layer thicknesses of only 1 micron. Nowadays (2010), the minimum thickness of the dielectric layer is about 0.5 microns. The field strength in the dielectric rises to a considerable 35,000 V/micron.
The size reduction of these capacitors is achieved by using more finely grained ceramic powder, thus making the ceramic layers thinner. In addition, the manufacturing process is made more precisely controlled, so that more and more of these thin ceramic layers can be stacked one above the other.
A report by Shoji Tsubota describes how, between 1995 and 2005, with ever thinner ceramic layers and more layers one above the other, the capacitance of a Y5V MLCC capacitor of size 1206 was increased from 4.7 μF to 100 μF. Meanwhile (2010), Taiyo Yuden has already introduced an X5R capacitor in the chip-size 0805 with a capacitance of 100 μF.
MLCC case sizes 
Surface-mount components like multi-layer ceramic chip capacitors are cheaper and a little bit smaller than their counterparts with leads, and they need no holes in the PCB, a second reduction of costs. They are designed to be handled by machines rather than by humans, another point to reduce the costs. For comparable handling, the electronics industry has standardized the rectangular package shapes and sizes of the chips. Nowadays multi-layer ceramic chip capacitors are manufactured in standard sizes. Because the chips first came out on the American market, the dimensions were standardized by EIA in units of "inches". A rectangular chip with the dimensions of 0.06 inch length and 0.03 inch width is coded as “0603”. This code up to now is international and in common use. But because now the leading standardisation organization is JEDEC (IEC/EN), a second, metric code has been generated. The EIA code and the metric equivalent of the common sizes of multilayer ceramic chip capacitors, and the dimensions in mm are shown in the following table. Missing from the table is the measure of the height "H". This is generally not listed, because the height of MLCC chips depends on the number of ceramic layers and thus on the capacitance of the capacitor. Normally, however, the amount of height H is not to exceed the dimension of the width W.
L x W
inch x inch
L × W
mm × mm
inch x inch
L × W
mm × mm
|01005||0.016 × 0.0079||0402||0.4 × 0.2||1806||0.18 × 0.063||4516||4.5 × 1.6|
|015015||0.016 x 0.016||0404||0.4 x 0.4||1808||0.18 x 0.079||4520||4.5 × 2.0|
|0201||0.024 × 0.012||0603||0.6 × 0.3||1812||0.18 × 0.13||4532||4.5 × 3.2|
|0202||0.02 x 0.02||0505||0.5 x 0.5||1825||0.18 x 0.25||4564||4.5 x 6.4|
|0302||0.03 x 0.02||0805||0.8 x 0.5||2010||0.20 × 0.098||5025||5.0 × 2.5|
|0303||0.3 x 0.03||0808||0.8 x 0.8||2020||0.20 x 0.20||5050||5.08 x 5.08|
|0504||0.05 x 0.04||1310||1.3 x 1.0||2220||0.225 x 0.197||5750||5.7 × 5.0|
|0402||0.039 × 0.020||1005||1.0 × 0.5||2225||0.225 x 0.25||5664/5764||5.7 x 6.4|
|0603||0.063 × 0.031||1608||1.6 × 0.8||2512||0.25 × 0.13||6432||6.4 × 3.2|
|0805||0.079 × 0.049||2012||2.0 × 1.25||2520||0.25 x 0.197||6450||6.4 x 5.0|
|1008||0.098 × 0.079||2520||2.5 × 2.0||2920||0.29 × 0.197||7450||7.4 × 5.0|
|1111||0.11 x 0.11||2828||2.8 x 2.8||3333||0.33 x 0.33||8484||8.38 x 8.38|
|1206||0.126 × 0.063||3216||3.2 × 1.6||3640||0.36 x 0.40||9210||9.2 x 10.16|
|1210||0.126 × 0.10||3225||3.2 × 2.5||4040||0.4 x 0.4||100100||10.2 x 10.2|
|1410||0.14 x 0.10||3625||3.6 x 2.5||5550||0.55 x 0.5||140127||14.0 x 12.7|
|1515||0.15 x 0.15||3838||3.81 x 3.81||8060||0.8 x 0.6||203153||20.3 x 15.3|
NME and BME metallization 
A particular problem in the production of multilayer ceramic chip capacitors at the end of the 1990s was a strong price increase of the metals used for the metallization of the electrodes and the terminals. Initially used, with regard to the high sintering temperatures of 1200 to 1400 °C, were the non-oxidizable noble metals silver and palladium. Both metals are expensive and greatly affect the price of the ceramic capacitors. This material composition is called "NME" (Noble Metal Electrode) metallization and lends very good electrical properties to ceramic capacitors, class 2 ones, too. But it drives, however, the cost per component upwards. These cost pressures led to the development of BME (Base Metal Electrode) metallization for the electrodes and the terminals using the much cheaper materials nickel and copper.
But with BME metallization, the electrical properties of ceramic capacitors were changed; for example, the voltage dependence of the class 2 ceramic capacitors X7R increased significantly (see picture). Even the loss factor and the impedance behavior of class 2 ceramic capacitors have been deteriorated by the BME metallization.
In class 2 ceramic capacitors, because of their use in applications where it is usually not very important for the stability of the electrical properties, these negative changes, for cost reasons, were finally accepted by the market, while the NME metallization was maintained in the class 1 ceramic capacitors.
MLCC capacitance ranges 
The capacitance of MLCC chips depends on the dielectric, the size and at the required voltage (rated voltage). The capacitance values start at about 1pF. The maximum capacitance value is determined by the momentary status of the production technique. For X7R that is 47 µF, for Y5V: 100 µF.
The picture right shows the maximum capacitance for class 1 and class 2 multilayer ceramic chip capacitors. The following three tables, for ceramics NP0/C0G, X7R and Y5V each, listed for each commonly used case size the maximum available capacitance value and the rated voltage. (status of the image and all tables: the beginning of 2010, manufacturers Murata, TDK, Kemet and AVX).
|Case size, EIA Code
Dimensions in mm
|25 V||100 pF||–||–||–||100 nF||–||-|
|50 V||–||1 nF||2.7 nF||22 nF||82 nF||–||220 nF|
|100 V||–||–||1 nF||4.7 nF||10 nF||47 nF||100 nF|
|250 V||–||–||680 pF||2.2 nF||6.8 nF||15 nF||47 nF|
|630 V||–||–||–||–||3.3 nF||6.8 nF||22 nF|
|3000 V||–||–||–||–||–||–||330 pF|
|Case size, EIA Code
Dimensions in mm
|6.3 V||–||–||–||2.2 µF||10 µF||–||–||–||-|
|10 V||–||–||10 nF||100 nF||2.2 µF||10 µF||–||22 µF||-|
|16 V||–||4.7 nF||100 nF||1.0 µF||4.7 µF||10 µF||22 µF||33 µF||47 µF|
|25 V||1.5 nF||3.3 nF||47 nF||470 nF||2.2 µF||4.7 µF||10 µF||22 µF||10 µF|
|50 V||–||–||10 nF||0.1 µF||0.47 nF||2.2 µF||3.3 µF||6.8 µF||-|
|100 V||–||–||4.7 nF||22 nF||0.47 µF||1.0 µF||2.2 µF||2.2 µF||4.7 µF|
|250 V||–||–||–||2.2 nF||22 nF||100 nF||220 nF||0.47 µF||1.0 µF|
|630 V||–||–||–||–||–||33 nF||68 nF||0.1 µF||0.22 µF|
|1000 V||–||–||–||–||–||4.7 nF||22 nF||47 nF||100 nF|
|2000 V||–||–||–||–||–||–||–||4.7 nF||10 nF|
|Case size, EIA Code
Dimensions in mm
|6.3 V||47 nF||1 µF||4.7 µF||22 µF||100 µF||100 µF||–||-|
|10 V||10 nF||1 µF||2.2 µF||10 µF||22 µF||47 µF||100 µF||-|
|16 V||–||470 nF||2.2 µF||4.7 µF||2.2 µF||22 µF||47 µF||100 µF|
|25 V||–||470 nF||2.2 µF||4.7 µF||10 µF||22 µF||47 µF||47 µF|
|50 V||–||220 nF||1.0 µF||2.2 µF||4.7 µF||10 µF||22 µF||22 µF|
|100 V||–||–||–||–||–||100 nF||–||470 nF|
Low-ESL styles 
In the region of its resonance frequency, a capacitor has the best decoupling properties for noise or interferences. The resonance frequency of a capacitor is determined by the inductance of the component. The smaller it is, the higher the resonance frequency. Because, especially in digital signal processing, the switching frequencies rising higher and higher, the demand for high frequencies decoupling or filter capacitors increases.
All inductive parts of a capacitor together are summarized in the “ESL”, the “equivalent series inductance L”. With a simple design change of the MLCC chip the ESL of the capacitor now can be reduced. For this the stacked electrodes, unlike the standard MLCC, are contacted on the longitudinal side with the connecting terminations. This reduces the distance that the charge carriers need to flow over the electrodes, which leads to a reduction in the summarized inductance of the component.
For the practical use of the capacitor, for example, the result for a X7R capacitor with 0.1 µF in the size of 0805, with a resonance frequency of about 16 MHz increases to about 22 MHz if the MLCC chip has a 0508-size with terminations at the longitudinal side.
Another possibility is to form the capacitor as an MLCC array. Here, several individual capacitors are built in a common housing. Connecting all capacitors in parallel, all inductances of the capacitors are connected in parallel, too. Thus reducing the resulting ESR value and in addition, the internal ohmic losses.
X2Y decoupling capacitor 
A standard multi-layer ceramic capacitor has many opposing electrode layers stacked inside connected with two outer terminations. The X2Y ceramic chip capacitor however is a 4 terminal chip device. It is constructed like a standard two-terminal MLCC out of the stacked ceramic layers with an additional third set of shield electrodes incorporated in the chip. These shield electrodes surround each existing electrode within the stack of the capacitor plates and are low ohmic contacted with two additional side terminations across to the capacitor terminations. The X2Y construction results in a three-node capacitive circuit that provides simultaneous line-to-line and line-to-ground filtering.
Capable of replacing 2 or more conventional devices, the X2Y ceramic capacitors are ideal for high frequency filtering or noise suppression of supply voltages in digital circuits, and can prove invaluable in meeting stringent EMC demands in dc motors, in automotive, audio, sensor and other applications.
The X2Y footprint results in lower mounted inductance. This is particularly of interest for use in high-speed digital circuits with clock rates of several 100 MHz and upwards. There the decoupling of the individual supply voltages on the circuit board is difficult to realize due to parasitic inductances of the supply lines. A standard solution with conventional ceramic capacitors requires the parallel use of many conventional MLCC chips with different capacitance values. Here X2Y capacitors are able to replace up to five equal-sized ceramic capacitors on the PCB. However, this particular type of ceramic capacitor is patented, so these components are still comparatively expensive.
Mechanical susceptibility 
Ceramic is on the one hand a very solid material; on the other hand, it breaks even at relatively low mechanical stress. MLCC chips as surface-mounted components are susceptible to flexing stresses since they are mounted directly on the substrate. They are stuck between soldered joints on the printed circuit board (PCB), and are often exposed to mechanical stresses, for example, if vibration or a bump impacts the circuit board. They are also more sensitive to thermal stresses than leaded components. Excess solder fillet height can multiply these stresses and cause chip cracking. Of all influencing factors, causing a mechanical shock stress to the PCB proved to be the most critical one. The reason is that forces induced by those kinds of stresses are more or less transmitted undampened to the components via the PCB and solder joints.
The capability of MLCC chips to withstand mechanical stress is tested by a so-called substrate bending test. Here, a test PCB with a soldered MLCC chip between two support points is bent by a punch at a path length of 1 to 3mm. The path length depends on the requirements that come out from the application. If no crack appears, the capacitors are able to withstand the wanted requirements. Cracks are usually detected by a short circuit or a change of the capacitance value in the deflected state.
The bending strength of the MLCC chip differs by the property of the ceramic, the size of the chip and the design of the capacitors. Without any special design features, NP0/C0G class 1 ceramic MLCC chips reach a typical bending strength of 2mm while larger types of X7R, Y5V class 2 ceramic chips achieved only a bending strength of approximately 1mm. Smaller chips, such as the size of 0402, reached in all types of ceramics larger bending strength values.
With special design features, particularly by special design of the electrodes and the terminations, the bending strength can be improved. For example, an internal short circuit arises by the contact of two electrodes with opposite polarity, which will be produced at the break of the ceramic in the region of the terminations. This can be prevented when the overlap surfaces of the electrodes are reduced. This is achieved e.g. by an "Open Mode Design“ (OMD). Here a break in the region of the terminations only reduce the capacitance value a little bit (AVX, KEMET).
"Flex-Termination" - MLCC chips, a flexible contact layer prevent a break of the ceramic.
With a similar construction called "Floating Electrode Design" (FED) or "Multi-layer Serial Capacitors" (MLSC), also, only capacitance reduction results if parts of the capacitor body break. This construction works with floating electrodes without any conductive connection to the termination. A break doesn’t lead to a short, only to capacitance reduction. However, both structures lead to larger designs with respect to a standard MLCC version with the same capacitance value.
The same volume with respect to standard MLCCs is achieved by the introduction of a flexible intermediate layer of a conductive polymer between the electrodes and the termination called "Flexible Terminations“ (FT-Cap) or "Soft Terminations“. In this construction, the rigid metallic soldering connection can move against the flexible polymer layer, and thus can absorb the bending forces, without resulting in a break in the ceramic.
RFI/EMI suppression ceramic capacitors 
Mainly because of their nonflammability in case of short circuit and their compatibility against high peak overvoltages (transient voltage), ceramic capacitors are often used as AC line filter capacitors for electromagnetic Interference (EMI) or radio Frequency Interference (RFI) suppression. These capacitors, also known as safety capacitors, are crucial components to reduce or suppress electrical noise caused by the operation of electrical or electronic equipment, while also providing limited protection against
Suppression capacitors are effective interference reduction components because their electrical impedance decreases with increasing frequency, so that at higher frequencies they short circuit electrical noise and transients between the lines, or to ground. They therefore prevent equipment and machinery (including motors, inverters, and electronic ballasts, as well as solid-state relay snubbers and spark quenchers) from sending and receiving electromagnetic and radio frequency interference as well as transients in across-the-line (X capacitors) and line-to-ground (Y capacitors) connections. X capacitors effectively absorb symmetrical, balanced, or differential interference. On the other hand, Y capacitors are connected in a line bypass between a line phase and a point of zero potential, to absorb asymmetrical, unbalanced, or common-mode interference.
EMI/RFI suppression capacitors are designed and installed so that any remaining interference or electrical noise does not exceed the limits of EMC directive EN 50081 Suppression components are connected directly to mains voltage semi-permanently for 10 to 20 years or more, and are therefore exposed to overvoltages and transients that could damage the capacitors. For this reason, suppression capacitors must comply with the safety and inflammability requirements of international safety standards such as the following:
- Europe: EN 60384-14,
- USA: UL 1414, UL 1283
- Canada: CSA C22.2, No.1, CSA C22.2, No.8
- China: CQC (GB/T 14472-1998)
RFI capacitors that fulfill all specified requirements are imprinted with the certification mark of various national safety standards agencies. For power line applications, special requirements are placed on the inflammability of the coating and the epoxy resin impregnating or coating the capacitor body. To receive safety approvals, X and Y powerline-rated capacitors are destructively tested to the point of failure. Even when exposed to large overvoltage surges, these safety-rated capacitors must fail in a fail-safe manner that will not endanger personnel or property.
Although up to now (2012) most of the ceramic capacitors used for EMI/RFI suppression are leaded ones for through-hole mounting on a PCB, the surface-mount technique is becoming more and more important. For this reason, in recent years a lot of MLCC chips for EMI/RFI suppression from different manufacturers have received approvals and fulfill all requirements given in the applicable standards.
Ceramic power capacitors 
Related to the above described smaller ceramic capacitors are the power ceramic capacitors. Although the materials used for large power ceramic capacitors mostly are very similar to those used for smaller ones, the ceramic capacitors with high to very high power or voltage ratings for applications in power systems, transmitters and electrical installations are often classified separately, for historical reasons. The standardization of ceramic capacitors for lower power is oriented toward electrical and mechanical parameters as components for use in electronic equipment. The standardization of power capacitors, contrary to that, is strongly focused on rules for the safety of personnel and equipment, given by the local regulating authority.
As modern electronic equipment gained the ability to handle power levels that were previously the exclusive domain of "electrical power" components, the distinction between the "electronic" and "electrical" power ratings has become less distinct. In the past, the boundary between these two families was approximately at a reactive power of 200 volt-amps, but modern power electronics can handle increasing amounts of power.
Power ceramic capacitors are mostly specified much higher than 200 volt-amps. The great plasticity of ceramic raw material and the high dielectric strength of ceramic delivers ideal solutions for many special applications and is the reason for the enormous diversity of styles within the family of power ceramic capacitors. These power capacitors have been on the market a very long time. They are produced according to the requirements as class 1 power ceramic capacitors with high stability and low losses or class 2 power ceramic capacitors with high volumetric efficiency.
Class 1 power ceramic capacitors are used for resonant circuit application in transmitter stations. Class 2 power ceramic capacitors are used for power circuit breakers, for power distribution lines, for high voltage power supply in laser-applications, for induction furnaces and in voltage-doubling circuits. Power ceramic capacitors can be supplied with high rated voltages in the range of 2 kV up to 100 kV.
The dimensions of these power ceramic capacitors can be very large for applications with high voltage or high power demand. At high power applications the losses of these capacitors can generate a lot of heat. For this reason some special styles of power ceramic capacitors have pipes for water-cooling.
Electrical characteristics 
Series-equivalent circuit 
All electrical characteristics of ceramic capacitors can be defined and specified by a series equivalent circuit composed out of an idealized capacitance and additional electrical components, which model all losses, and inductive parameters of a capacitor. In this series-equivalent circuit the electrical characteristics of a capacitors is defined by
- C, the capacitance of the capacitor,
- Rinsul, the insulation resistance of the dielectric, not to be confused with the insulation of the housing
- RESR, the equivalent series resistance, which summarizes all ohmic losses of the capacitor, usually abbreviated as “ESR”.
- LESL, the equivalent series inductance, which is the effective self-inductance of the capacitor, usually abbreviated as “ESL”.
The use of a series equivalent circuit instead of a parallel equivalent circuit is harmonized by the international generic specification for capacitors IEC/EN 60384-1.
Capacitance standard values and tolerances 
The “rated capacitance” CR or “nominal capacitance” CN is the value for which the capacitor has been designed. The actual capacitance of capacitors depends on the measuring frequency and the ambient temperature. Standardized conditions for capacitors are a low-voltage AC measuring method at a temperature of 20°C with frequencies of
- Class 1 ceramic capacitors
- CR ≤ 100 pF at 1 MHz, measuring voltage 5 V
- CR > 100 pF at 1 kHz, measuring voltage 5 V
- Class 2 ceramic capacitors
- CR ≤ 100 pF at 1 MHz, measuring voltage 1 V
- 100 pF < CR ≤ 10 µF at 1 kHz, measuring voltage 1 V
- CR > 10 µF at 100/120 Hz, measuring voltage 0.5 V
Capacitors are available in different of geometrically increasing preferred values whose values are specified in the E series standards specified in IEC/EN 60063. According to the number of values per decade, these were called the E3, E6, E12, E24, etc. series. The range of units used to specify capacitor values has expanded to include everything from pico- (pF) over nano- (nF) and microfarad (µF) to farad (F).
The percentage of allowed deviation of the capacitance from the rated value is called capacitance tolerance. The actual capacitance value of a capacitor should be within the tolerance limits, or the capacitor is out of specification. For abbreviated marking in tight spaces, a letter code for each tolerance is specified in IEC/EN 60062.
|CR > 10 pF||Letter code||CR < 10 pF||Letter code|
The required capacitance tolerance is determined by the particular application. The narrow tolerances of E24 to E96 will be used for high-quality class 1 capacitors in circuits like precision oscillators and timers. On the other hand, for general applications such as non-critical filtering or coupling circuits, for class 2 capacitors the tolerance series E12 down to E3 are sufficient.
Temperature dependence of capacitance 
The capacitance of a capacitor varies with the temperature. The different dielectrics of the many capacitor types show great differences in the temperature dependence of the capacitance. The temperature coefficient is expressed in parts per million (ppm) per degree Celsius for class 1 ceramic capacitors or in percent (%) over the total temperature range for class 2 capacitors.
|Type of capacitor,
|Ceramic capacitors class 1
|±30 ppm/K (±0.5%)||−55…+125 °C|
|Ceramic capacitors class 2,
|Ceramic capacitors class 2,
|+22% / −82%||−30…+85 °C|
Frequency dependence of capacitance 
Most of all of the different discrete capacitor types have more or less frequency changes with increasing frequencies. The dielectric strength of class 2 ceramic and plastic film diminishes with rising frequency. Therefore their capacitance value decreases with increasing frequency. This phenomenon for ceramic class 2 dielectrics is related to the dielectric relaxation in which the time constant of the electrical dipoles is the reason for the frequency dependence of permittivity. The graph on the right hand side show typical frequency behavior of the capacitance for class 2 ceramic capacitors in contrast to NP0-class 1 capacitors.
Voltage dependence of capacitance 
Capacitors may also change capacitance with applied voltage. This effect is more prevalent in class 2 ceramic capacitors. The ferroelectric material of class 2 capacitors depends on the applied voltage. The higher the applied voltage, the lower the permittivity. The change of capacitance can drop down to values of -80% of the value measured with the standardized measuring voltage of 0.5 or 1.0 V. This behavior is a small source of nonlinearity using class 2 ceramic capacitors in low-distortion filters and other analog applications and in audio applications this can be the reason for harmonic distortions.
Voltage proof 
For each dielectric material in capacitors, usually could be specified a physically conditioned dielectric strength or a breakdown voltage per thickness of the material. This is not possible with ceramic capacitors. The breakdown voltage of a ceramic dielectric layer may vary depending on the composition of the electrode material and the sintering conditions of the ceramic up to the factor 10. It requires a high degree of precision and control of the various process parameters to keep the scattering of electrical properties for today's very thin ceramic layers within specifiable limits
The voltage proof of ceramic capacitors is specified as rated voltage (UR). This is the maximum DC voltage that may be continuously applied to the capacitor up to the upper category temperature. This guaranted voltage proof will be tested with style depending test voltages shown in the table right.
Furthermore, in periodic life time tests (endurance tests) the voltage proof of ceramic capacitors will be tested with increased test voltage (120 to 150% of UR) to ensure the safe construction of the capacitors.
|Style||Rated voltage||Test voltage|
|UR ≤ 100 V||2.5 UR|
|100 V < UR ≤ 200 V||1.5 UR + 100 V|
|200 V < UR ≤ 500 V||1.3 UR + 100 V|
|500 V < UR||1.3 UR|
|UR ≤ 500 V||2.5 UR|
|UR > 500 V||1.5 UR + 500 V|
The frequency depending AC resistance of a capacitor is called impedance and is the complex ratio of the voltage to the current in an AC circuit. Impedance extends the concept of ohm's law to AC circuits, and possesses both magnitude and phase at a particular frequency unlike resistance, which has only magnitude.
The impedance is a measure of the ability of the capacitor to pass alternating currents. In this sense the impedance can be used like Ohms law
to calculate either the peak or the effective value of the current or the voltage.
As shown in the series-equivalent circuit of a capacitor the real component include an ideal capacitor , an inductance and a resistor .
To calculate the impedance now the resistance and the both reactances have to be added geometrically
wherein the capacitive reactance (Capacitance) is
and an inductive reactance (Inductance) is
In the special case of resonance, in which the both reactive resistances have the same value (), then the impedance will only be determined by .
The data sheets of ceramic capacitors only specify the magnitude of the impedance . The typical curve of the impedance shows that with increasing frequency, the impedance decreases, down to a minimum. The lower the impedance, the more easily alternating currents can be passed through the capacitor. At the minimum point of the curve, the point of resonance, where XC has the same value than XL, the capacitor has the lowest impedance value. Here only the ESR determines the impedance. With frequencies above the resonance the impedance increases again due to the ESL of the capacitor. The capacitor becomes to an inductance.
ESR, dissipation factor, and quality factor 
The summarized losses in ceramic capacitors are ohmic AC losses. DC losses will be specified as "leakage current" or “insulating resistance” and are negligible for an AC specification. These AC losses are nonlinear, and may depend on frequency, temperature, age, and for some special types, on humidity. The losses result from two physical conditions,
- the line losses with the internal supply line resistances, the contact resistance of the electrode contact, the line resistance of the electrodes
- the dielectric losses out of the dielectric polarzation
The largest share of these losses in larger capacitors is usually the frequency dependent ohmic dielectric losses. Regarding the IEC 60384-1 standard, the ohmic losses of capacitors should be measured at the same frequency used to measure the capacitance. These are:
- 100 kHz, 1 MHz (preferred) or 10 MHz for ceramic capacitors with CR ≤ 1 nF:
- 1 kHz or 10 kHz for ceramic capacitors with 1 nF < CR ≤ 10 μF
- 50/60 Hz or 100/120 Hz for ceramic capacitors with CR > 10 μF
The measuring results of the summarized resistive losses of a capacitor may be specified either as equivalent series resistance (ESR), as dissipation factor(DF, tan δ), or as quality factor (Q), depending on the application requirements for the capacitor types.
Class 2 ceramic capacitors are mostly specified with the dissipation factor tan δ. The dissipation factor is determined as the tangent of the reactance - and the ESR, and can be shown as the angle δ between imaginary and the impedance axis in the above vector diagram, see paragraph “Impedance”.
If the inductance is small, the dissipation factor can be approximated calculated as:
Class 1 ceramic capacitors with very low losses are specified with a dissipation factor and additional often with a quality factor (Q). The quality factor is defined as the reciprocal value of the dissipation factor.
The Q factor represents the effect of electrical resistance, and characterizes a resonator's bandwidth relative to its center or resonant frequency . A high Q value is for resonant circuits a mark of the quality of the resonance.
In accordance with the applicable standards IEC 60384-8/-21/-9/-22 ceramic capacitors may not exceed the following dissipation factors
of the ceramic
|100 ≥ α > −750||tan δ ≤ 15 • 10−4|
|−750 ≥ α > −1500||tan δ ≤ 20 • 10−4|
|−1500 ≥ α > −3300||tan δ ≤ 30 • 10−4|
|−3300 ≥ α > −5600||tan δ ≤ 40 • 10−4|
|≤ −5600||tan δ ≤ 50 • 10−4|
|For capacitance values < 50 pF
the dissipation factor may be larger
of the capacitor
|≥ 10 V||tan δ ≤ 350 • 10−4|
|For capacitance values < 50 pF
the dissipation factor may be larger
The ohmic losses of ceramic capacitors are frequency, temperature, and voltage dependent. Additionally, class 2 capacitors are time dependent because of aging. The different ceramic materials have different changes in the losses over the temperature range and the operating frequency. The changes in class 1 capacitors are in the single-digit range while class 2 capacitors have much higher changes.
HF use, inductance (ESL) and self-resonant frequency 
For any discrete capacitor, there is a frequency above DC at which it ceases to behave as a pure capacitance. This frequency where XC is as high as XL is called the self-resonant frequency. The self-resonant frequency is the lowest frequency at which the impedance passes through a minimum. For any AC application the self-resonant frequency is the highest frequency capacitors can be used as a capacitive component. With frequencies above the resonance the impedance increases again due to the ESL of the capacitor. The capacitor becomes to an inductance. ESL in industrial capacitors is mainly caused by the leads and internal connections used to connect the plates to the outside world. Larger capacitors tend to higher ESL than small ones because the distances to the plate are longer and every millimeter counts as an inductance. Leaded ceramic capacitors are already out of their smaller capacitance values suitable for higher frequencies up to several 100 MHz. MLCC chips have, due to their construction without any leads and proximity to the electrodes, significantly lower parasitic inductance than leaded types, which makes them suitable for higher frequency applications. A further reduction of the parasitic inductance is achieved by contacting the electrodes on the longitudinal side of the chip instead of the lateral side. The "face-down" construction associated with the multi-anode technology, see paragraph #Low-ESL styles. Thus increase the resonance frequency of the capacitor and, for example, can follow the constantly increase of the switching speed of digital circuits where MLCCs are crucial components for decoupling high-speed logic circuits from the power supply.
Sample self-resonant frequencies for one set of NP0/C0G and one set of X7R ceramic capacitors are:
|10 pF||100 pF||1 nF||10 nF||100 nF||1 µF|
|C0G (Class 1)||1550 MHz||460 MHz||160 MHz||55 MHz|
|X7R (Class 2)||190 MHz||56 MHz||22 MHz||10 MHz|
Note that this is slightly surprising, since C0G manufacturers typically claim (without giving numbers) that C0Gs have better frequency response than X7Rs, whereas the reverse appears to be true. It makes sense, however, since class 2 capacitors are much smaller than class 1, so they ought to have lower parasitic inductance.
Capacitor technologies with higher self-resonant frequencies like MOS capacitors or silicon capacitors tend to be expensive.
In ferroelectric class 2 ceramic capacitors a decreasing of the capacitance over time takes place. This behavior is called “aging”. The aging occurs in ferroelectric dielectrics, where domains of polarization in the dielectric contribute to the total polarization. By degradation of the polarized domains in the dielectric the permittivity decreases over time so that the capacitance of class 2 ceramic capacitors decreases as the component ages.  The aging follows a logarithmic law. This defines the decrease of capacitance as a percentage for a time decade after the soldering recovery time at a defined temperature, for example, in the period from 1 to 10 hours at 20 °C. As the law is logarithmic, the percentage loss of capacitance will twice between 1 h and 100 h and 3 times between 1 h and 1000 h and so on. So the aging is fastest near the beginning of life of the component, and the capacitance value stabilizes over time.
The grade of aging of class 2 ceramic capacitors mainly depends on the materials used. A rule of thumb is, the higher the temperature dependence of the ceramic, the higher the aging percentage. The typical aging of X7R ceramic capacitors is about 2.5% per time decade The aging rate of Z5U ceramic capacitors is significantly higher and can be up to 7% per time decade.
The aging process of class 2 ceramic capacitors may be reversed by heating the component above the Curie point.
Class 1 ceramic capacitors do not have a ferroelectric aging like Class 2 ceramic capacitors. But environmental influences such as higher temperature, high humidity and mechanical stress can, over a longer period of time, lead to a small irreversible change in the capacitance value sometimes called aging, too. The change of capacitance value for P 100 and N 470 Class 1 ceramic capacitors is lower than 1%, for the for capacitors with N 750 to N 1500 ceramics it is ≤ 2%.
Insulation resistance and self-discharge constant 
The resistance of the dielectric of a capacitor is never truly infinite, leading to some level of DC “leakage current”, which is the reason for self-discharging of a charged capacitor over the time. For ceramic capacitors this resistance placed in parallel with the capacitor in the series-equivalent circuit of capacitors is called “insulation resistance Rins”. The insulation resistance must not be confused with the outer isolation of the component with respect to the environment.
The time curve of self-discharge over the insulation resistance with decreasing capacitor voltage follows the formula
With the stored DC voltage and the self-discharge constant
That means, after the time of the capacitor voltage has dropped to 37% of the initial value.
The insulation resistance given in the unit MΩ (10^6 Ohm) as well as the self-discharge constant in the unit second (s) is an important parameter for the quality of the dielectric insulation between the electrodes of a ceramic capacitors. These time values are important, for example, when a capacitor is used as time-determining component for time relays or for storing a voltage value as in a sample and hold circuits or operational amplifiers.
In accordance with the applicable standards, Class 1 ceramic capacitors have an Rins ≥ 10,000 MΩ for capacitors with CR ≤ 10 nF or τs ≥ 100 s for capacitors with CR > 10 nF. Class 2 ceramic capacitors have an Rins ≥ 4,000 MΩ for capacitors with CR ≤ 25 nF or τs ≥ 100 s for capacitors with CR > 25 nF.
The insulation resistance and thus the self-discharge time constant are temperature dependent and decrease with increasing temperature at about 1 MΩ per 60 °C.
Dielectric absorption (soakage) 
Dielectric absorption is the name given to the effect by which a capacitor, which has been charged for a long time, discharges only incompletely when briefly discharged. Although an ideal capacitor would remain at zero volts after being discharged, real capacitors will develop a small voltage coming from time-delayed dipole discharging, a phenomenon that is also called dielectric relaxation, "soakage" or "battery action".
|Type of capacitor||Dielectric Absorption|
|Class-1 ceramic capacitors, NP0||0.3 to 0.6%|
|Class-2 ceramic capacitors, X7R||2.0 to 2.5%|
In many applications of capacitors dielectric absorption is not a problem but in some applications, such as long-time-constant integrators, sample-and-hold circuits, switched-capacitor analog-to-digital converters, and very low-distortion filters, it is important that the capacitor does not recover a residual charge after full discharge, and capacitors with low absorption are specified. The voltage at the terminals generated by the dielectric absorption may in some cases possibly cause problems in the function of an electronic circuit or can be a safety risk to personnel. In order to prevent shocks, most very large capacitors are shipped with shorting wires that need to be removed before they are used.
All ferroelectric materials exhibit piezoelectricity, and have a piezoelectric effect. Because class 2 ceramic capacitors using ferroelectric ceramics as dielectric, these types of capacitors may have electrical effects called microphonics. Microphonics or microphony describes the phenomenon wherein electronic components transform mechanical vibrations into an undesired electrical signal (noise). Mechanical forces coming from shocks or vibration may be absorbed by the ferroelectric dielectric changing the thickness a little bit, and moving the distance of the electrodes to each other, causing the capacitance to vary, in turn inducing an AC current. The resulting interference is especially problematic in audio applications, potentially causing feedback or unintended recording.
In the reverse microphonic effect, the varying electric field between the capacitor plates exerts a physical force, moving them as a speaker. High current impulse loads or high ripple currents can generate audible acoustic sound coming from the capacitor itself, but drains energy and stresses the dielectric.
Ceramic capacitors behavior from soldering 
Ceramic capacitors may have changes of their electrical parameters due to soldering stress. The heat of the solder bath, especially for SMD styles, can cause in ceramic capacitors changes of the contact resistance between terminals and electrodes. For ferroelectric class 2 ceramic capacitors the soldering temperature is above the Curie point. The polarized domains in the dielectric are going back and the aging process of class 2 ceramic capacitors is starting again. Hence for all ceramic capacitors after soldering a recovery time of approximately 24 hours should be noted. After recovery some electrical parameters like capacitance value, ESR, leakage current are changed irreversibly. The changes are in the lower percentage range depending on the style of capacitor.
Additional information 
Features and disadvantages of ceramic capacitors 
For features and disadvantages of ceramic capacitors see main article Types of capacitor#Capacitor features comparisons
The tests and requirements to be met by capacitors for use in electronic equipment for approval as standardized types are set out in the generic specification IEC/EN 60384-1 and the following sectional specifications for ceramic capacitors:
- IEC 60384-8, Fixed capacitors of ceramic dielectric, Class 1
- IEC 60384-9, Fixed capacitors of ceramic dielectric, Class 2
- IEC 60384-21, Fixed surface mount multilayer capacitors of ceramic dielectric, Class 1
- IEC 60384-22, Fixed surface mount multilayer capacitors of ceramic dielectric, Class 2
Tantalum capacitor replacement use 
Multilayer ceramic capacitors are increasingly used to replace tantalum and low capacitance aluminium electrolytic capacitors in applications such as bypass or high frequency switched-mode power supplies as their cost, reliability and size becomes competitive. In many applications, their low ESR allows the use of a lower nominal capacitance value.
Imprinted markings 
Ceramic capacitors, like most other electronic components and if space enough exists, have imprinted markings to indicate the manufacturer, the type, their electrical and thermal characteristics, and their date of manufacture. In the ideal case, if they are large enough, the capacitor will be marked with:
- manufacturer's name or trademark;
- manufacturer's type designation;
- rated capacitance;
- tolerance on rated capacitance
- rated voltage and nature of supply (AC or DC)
- climatic category or rated temperature;
- year and month (or week) of manufacture;
- certification marks of safety standards (for safety EMI/RFI suppression capacitors)
Smaller capacitors use a shorthand notation, to display all the relevant information in the limited space. The most commonly used format is: XYZ J/K/M VOLTS V, where XYZ represents the capacitance (calculated as XY × 10Z pF), the letters J, K or M indicate the tolerance (±5%, ±10% and ±20% respectively) and VOLTS V represents the working voltage.
- A capacitor with the following text on its body: 105K 330V has a capacitance of 10 × 105 pF = 1 µF (K = ±10%) with a working voltage of 330 V.
- A capacitor with the following text: 473M 100V has a capacitance of 47 × 103 pF = 47 nF (M = ±20%) with a working voltage of 100 V.
Capacitance, tolerance, and date of manufacture also can be identified with short code according to IEC/EN 60062. Examples of short-marking of the rated capacitance (microfarads):
- µ47 = 0.47 µF, 4µ7 = 4.7 µF, 47µ = 47 µF
The date of manufacture is often printed in accordance with international standards in abbreviated form.
- Version 1: coding with year/week numeral code, "1208" is "2012, week number 8".
- Version 2: coding with year code/month code,
Year code: "R" = 2003, "S"= 2004, "T" = 2005, "U" = 2006, "V" = 2007, "W" = 2008, "X" = 2009, "A" = 2010, "B" = 2011, "C" = 2012, "D" = 2013 e.t.c.
Month code: "1" to "9" = Jan. to Sept., "O" = October, "N" = November, "D" = December
"X5" is then "2009, May"
For very small capacitors like MLCC chips no marking is possible anymore. Here only the traceability of the manufacturers can ensure the identification of a type.
Colour coding 
The identification of modern capacitors has known no detailed color coding for more than 25 years .
Manufacturers and products 
An overview of worldwide operating manufacturers and their product ranges as of 2012 is given in the following table:
≥ 1 kV
|AVX/Kyocera Ltd., ATC, American Technical Ceramics||X||X||X||X||–||–|
|Dover Technologies (CMP) Novacap, Syfer)||X||X||X||X||X||–|
|Hua Feng Electronics (CINETECH)||X||X||–||–||–||–|
|Johanson Dielectrics Inc.||X||X||X||X||–||–|
|KEMET Corporation, Arcotronics, Evox Rifa||X||X||X||X||–||X|
|KOA Corporation Speer Electronics, Inc.||X||–||X||–||X||–|
|Morgan Electro Ceramics||–||–||X||–||–||X|
|Murata Manufacturing Co. Ltd.||X||X||X||–||X||–|
|NCC, Europe Chemi-Con||X||X||X||–||–||–|
|Passive Plus Inc Hi-Q/Low ESR Caps||X||X||X||-||X||X|
|Prosperity Dielectrics Co. (PDC)||X||X||–||X||–||–|
|Samsung Electro-Mechanics Co. Ltd.||X||X||–||–||X||–|
|Samwha Capacitor Group||X||X||X||–||X||–|
|TDK-Epcos (TDK-EPC Corporation)||X||X||X||X||X||X|
|Union Technology Corporation (UTC)||X||X||X||X||X||–|
|Vishay Intertechnology Inc., Vitramon, CeraMite||X||X||X||X||–||X|
See also 
- J. Ho, T. R. Jow, S. Boggs, Historical Introduction to Capacitor Technology, PDF 
- J. Ho, T. R. Jow, S. Boggs, Historical Introduction to Capacitor Technology, PDF 
- Murata, Technical Report, Evolving Capacitors
- J. Ho, T. R. Jow, S. Boggs, Historical Introduction to Capacitor Technology, PDF 
- TRS Technologies: Advanced High Energy Capacitors (Zuletzt geprüft 17. Dezember 2012)
- Chroma Technology Co., Ltd., CLASS III – General Purpose High-K Ceramic Disk Capacitors 
- Kemet: Ceramic leaded Capacitors F-3101F 06/05
- Otto Zinke, Hans Seither (2002) (in German), Widerstände, Kondensatoren, Spulen und ihre Werkstoffe (2. ed.), Berlin: Springer, ISBN 3-540-11334-7
- W. S. Lee, J. Yang, T. Yang, C. Y. Su, Y. L. Hu, Yageo: Ultra High-Q NP0 MLCC with Ag inner Electrode for Telecommunication Application. In: Passive Components Industry, 2004, page 26ff 
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- Yellow Stone corp. Semiconductive (Barrier Layer Type) Capacitor , Class III : Semi- conductive type 
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