Test register: Difference between revisions
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Two test registers, '''TR6''' and '''TR7''', were provided for the purpose of testing. TR6 was the test command register, and TR7 was the test data register. These registers were accessed by variants of the [[MOV (x86 instruction)|MOV]] instruction. A test register may either be the source operand or the destination operand. The MOV instructions are defined in both [[real-address mode]] and [[protected mode]]. The test registers are privileged resources. In protected mode, the MOV instructions that access them can only be executed at [[privilege level]] 0. An attempt to read or write the test registers when executing at any other privilege level causes a general protection exception. Also, those instructions generate invalid opcode exception on any CPU newer than 80486. |
Two test registers, '''TR6''' and '''TR7''', were provided for the purpose of testing. TR6 was the test command register, and TR7 was the test data register. These registers were accessed by variants of the [[MOV (x86 instruction)|MOV]] instruction. A test register may either be the source operand or the destination operand. The MOV instructions are defined in both [[real-address mode]] and [[protected mode]]. The test registers are privileged resources. In protected mode, the MOV instructions that access them can only be executed at [[privilege level]] 0. An attempt to read or write the test registers when executing at any other privilege level causes a general protection exception. Also, those instructions generate invalid opcode exception on any CPU newer than 80486. |
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The instruction is encoded in two ways, depending on the flow of data. Moving data from a general purpose register into a test register is encoded as <code>0F 26 /r</code> (with <code>r/m</code> being the GPR, and <code>reg</code> being the test register). Moving data the other way (i.e. from the test register into a general purpose register) is encoded as <code>0F 24 /r</code> (with <code>r/m</code> being the GPR, and <code>reg</code> being the test register)<ref>{{Cite book|url=https://manualzz.com/doc/51363286/intel-dj-equipment-80386-user-manual|title=Introduction to the 80386 Including the 80386 Data Sheet|date=April 1986|publisher=[[Intel]]|pages=122}}</ref>. |
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TR6-7 from Register (i.e. MOV TRn, r32) is encoded as 00001111 00100110 11 eee reg (i.e. 0f 26 /r). Register from TR6-7 (i.e. MOV r32, TRn) is encoded as 00001111 00100100 11 eee reg (i.e. 0f 24 /r).<ref>{{Cite web|date=March–April 1986|title=Introduction to the 80386: Including the 80386 Data Sheet|url=https://manualzz.com/doc/51363286/intel-dj-equipment-80386-user-manual|url-status=live|archive-url=https://web.archive.org/web/20210325023754/https://s3p.manualzz.com/store/data/051363286.pdf?k=AwAAAXhnPHQ-AAACWGD_0SQaf8HFbyIZajH7VDm2suPn|archive-date=2021-03-25|access-date=2021-03-25|website=manualzz.com|publisher=Intel}}</ref> |
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==See also== |
==See also== |
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Revision as of 15:48, 15 May 2021
A test register, in the Intel 80386 and Intel 80486 processor, was a register used by the processor, usually to do a self-test. Most of these registers were undocumented, and used by specialized software. The test registers were named TR3 to TR7. Regular programs don't usually require these registers to work. With the Pentium, the test registers were replaced by a variety of model-specific registers (MSRs).
Two test registers, TR6 and TR7, were provided for the purpose of testing. TR6 was the test command register, and TR7 was the test data register. These registers were accessed by variants of the MOV instruction. A test register may either be the source operand or the destination operand. The MOV instructions are defined in both real-address mode and protected mode. The test registers are privileged resources. In protected mode, the MOV instructions that access them can only be executed at privilege level 0. An attempt to read or write the test registers when executing at any other privilege level causes a general protection exception. Also, those instructions generate invalid opcode exception on any CPU newer than 80486.
The instruction is encoded in two ways, depending on the flow of data. Moving data from a general purpose register into a test register is encoded as 0F 26 /r (with r/m being the GPR, and reg being the test register). Moving data the other way (i.e. from the test register into a general purpose register) is encoded as 0F 24 /r (with r/m being the GPR, and reg being the test register)[1].
See also
References
- ^ Introduction to the 80386 Including the 80386 Data Sheet. Intel. April 1986. p. 122.
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