Three-dimensional integrated circuit

In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip with two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this promising technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.

3D ICs vs. 3D packaging

3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate with off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC is a single chip. All components on the layers communicate with on-chip signaling, whether vertically or horizontally. Essentially, a 3D IC bears the same relation to a 3D package that an SoC bears to a circuit board.

Manufacturing technologies

As of 2008 there are four ways to build a 3D IC:

Monolithic – Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring. This monolithic 3D-IC technology has been researched at Stanford university under a DARPA sponsored grant.

Wafer-on-Wafer – Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicon vias” (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad.

Die-on-Wafer – Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dies are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dies may be added to the stacks before dicing.

Die-on-Die – Electronic components are built on multiple dies, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding.

Benefits

3D ICs offer many significant benefits, including:

Footprint – More functionality fits into a small space. This extends Moore’s Law and enables a new generation of tiny but powerful devices.

Speed – The average wire length becomes much shorter. Because propagation delay is proportional to the square of the wire length, overall performance increases.

Power – Keeping a signal on-chip reduces its power consumption by ten to a hundred times. Shorter wires also reduce power consumption by producing less parasitic capacitance. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.

Design – The vertical dimension adds a higher order of connectivity and opens a world of new design possibilities.

Cost - Partitioning a large chip to be multiple smaller dies with 3D stacking could potentially improve the yield and reduce the fabrication cost.

Heterogeneous integration – Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Even more interesting, components with completely incompatible manufacturing could be combined in a single device.

Circuit security - The stacked structure hinders attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.

Bandwidth - 3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor. Wide buses in turn alleviate the memory wall problem.

Challenges

Because this technology is new it carries new challenges, including:

Cost - Each active plane of a 3DIC has its own 2D manufacturing cost. In the fully stacked product, the manufacturing costs obviously add up.

Yield - Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects must be avoided or repaired.

Heat - Thermal buildup within the stack must be prevented or dissipated. This is an inevitable issue as electrical proximity goes hand-in-hand with thermal proximity.

Design complexity - Taking full advantage of 3D requires intricate and elegant multi-level designs. Chip designers will need new CAD tools to address the 3D paradigm.

Lack of standards - There are currently no standards for TSV-based 3DIC packaging. In addition, there are still many integration options which are being explored, such as via-last, via-first, via-middle, etc.

Lack of relevance after insertion - With the use of TSVs, bandwidth and speed and power consumption are no longer dominated by the long-distance interconnects, but by the performance of individual discrete components on each individual chip active layer. Any further improvements in the 3DIC package or interconnect technology will not be obviously noticed until improvements to the various component technologies are carried out.

Heterogeneous integration supply chain - In heterogeneously integrated systems, the delay of one part from one of the different parts suppliers delays the delivery of the whole product, and so delays the revenue for each of the 3DIC part suppliers.

Lack of clearly defined ownership - It is unclear who should own the 3DIC integration and packaging/assembly. It could be assembly houses like ASE or the product OEMs.

Further reading

• Philip Garrou, Christopher Bower, Peter Ramm: Handbook of 3D Integration, Technology and Applications of 3D Integrated Circuits 2nd Edition. Wiley-VCH, Weinheim 2008, ISBN: 978-3527-32034-9.
• Yuan Xie, Jason Cong, Sachin Sapatnekar: Three-Dimensional Integrated Circuit Design: Eda, Design And Microarchitectures, Publisher: Springer, ISBN: 1441907831,9781441907837,978-1441907837, Publishing Date: Dec 2009

External links

Potential Applications

• 2007, 3D FPGA: [1] "Performance Benefits of Monolithically Stacked 3D-FPGA (invited)", Mingjie Lin, Abbas El Gamal, Yi-chang Lu, and Simon Wong, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, Volume 26, Issue 2.

Early products

• 2001, Monolithic write-once memory: “Matrix preps 64-Mbyte write-once memory” EE Times
• 2004, Wafer-to-wafer RAM: “MagnaChip, Tezzaron form partnership for 3D chips” EE Times
• 2007, Die-to-wafer focal plane array: “Ziptronix, Raytheon Prove 3-D Integration of 0.5 µm CMOS Device” Semiconductor International

Organizations

• 3D-IC Alliance
• EMC3D
• RTI “TechVenture” Forum
• SEMATECH
• IMEC
• Amkor Technology 3D & Stacked-Die Packaging Technology Solutions

Selected press references

• 2003, EE Design: “Three-dimensional SoCs perform for future”
• 2004, EDN: “3D Interconnect Technology Coming to Light”
• 2005, Semiconductor International: “Three-Dimensional ICs Solve the Interconnect Paradox”
• 2006, Solid State Technology: “Mapping progress in 3D IC integration”
• 2007, Nikkei Electronics Asia: “Vertical Stacking to Redefine Chip Design”
• 2008, Semiconductor International: “How Might 3-D ICs Come Together?”
• 2009, Advanced Packaging: “Signs of 3D Maturity”