Talk:PCI Express

Power options

I made these changes [1]. As I mentioned in the hidden comment, the claim that PCI express 2.x adds support for 150W per slot seems to be common in some sources, particularly those from around the time of release. However a number of more recent sources either directly dispute this, or don't mention any such change. This includes some which refer to presentations from PCI-sig. The source used there was fairly poor. What it basically said was the card probably uses more then 75W and it doesn't have a 6 pin connector so it must be relying on the (alleged) ability of the PCI express 2.x slot to provide 150W. Except that they didn't actual try to estimate power consumption of the card and when they did measure power consumption under load it was with Furmark, and evidence suggests both GPU and card manufacturers consider Furmark may impose power usage requirements beyond what they spec for. (Estimates and official specs for the 6850 suggest power consumption was high enough it's unlikely the card is under 75W but you can never know without testing.) More importantly, there's no actual evidence to suggest the card is compliant with the spec. Perhaps the manufacturer felt enough motherboards would work without issue even if they were exceeding the spec or perhaps the manufacturer was similarly confused by the rumours. Either way the reference didn't come across as particularly reliable.

As I mentioned, there are quite a few references including those using presentation or other info from PCI-sig suggesting that the 75W per slot limitation remains in 2.x and even the 3.0 spec. While ORry, I've had a look at this info myself and even had a quick check at the PCI express spec (doesn't ask how I got it) and couldn't find any info of a 150W slot standard. I'm not sure where the 150W per slot claim came from, I've seen some suggestion there were plans for 150W per slot initially but this was abandoned (and perhaps considered again for 3 but again abandoned.) Alternatively, it's also notable that occasionally PCI-sig refer to power per slot when they actually mean the maximum power a single card can draw from all sources incluing the extra connectors and not solely from the PCI express motherboard connectors. I don't believe the claim 150W per slot was introduced with PCI express 2.1 even makes sense since from what I can tell the 2.0 spec was introduced together with the 2.0 Card Electromechanical Specification. There's no such thing as a 2.1 CEM spec. And while I'm not an expert, I don't see how the you could add support for 150W from the slot without updating the CEM (well unless it was already speced in the CEM but not in the main spec for some reason although both the 2.0 CEM and 225/300W high power CEM only seem to mention 75W from the slot).

What does seem clear is that initially PCI-express only allowed 150W total (75W from the slot and 75W from the 6 pin) but with the 2.0 standard, the option for 225W and 300W were introduced with the addition of the 8 pin connector. According to PCI-sig, 225W can either come from an 8pin plus 75W from the slot or two 6 pin with 75W each and 75W from the slot or one 6 pin and one 8 pin but still 75W from each and 75W from the slot. 300W uses 75W from the slot, a 8 pin connector for 150W and a 6 pin connector for 75W (the option for 3 6 pin is also mentioned but it's stated as a unpreferred option). I have come across any mention of getting 150W fron the slot from PCI-sig themselves. Note that while some cards with 375W exist using two 8 pin connectors and 75W from the slot, these aren't specified in the spec. This increaee in power options with PCI express 2 may be one source of the confusion. From my research, it seems to me in recent times we're another source of confusion hence my demands for high quality referencing. Really I think we need references from an expert (perhaps a hardware engineer) who has referred to the PCI-sig specs themselves not simple hardware review sites.

Nil Einne (talk) 07:21, 23 November 2012 (UTC)

Transfer Speeds

Is this right? Does the B->T conversion really scale like that? What is that unit anyway?:

Per lane (each direction):

• v1.x: 250 MB/s (2.5 GT/s)
• v2.x: 500 MB/s (5 GT/s)
• v3.0: 1 GB/s (8 GT/s)
• v4.0: 2 GB/s (16 GT/s)

16 lane slot (each direction):

• v1.x: 4 GB/s (40 GT/s)
• v2.x: 8 GB/s (80 GT/s)
• v3.0: 16 GB/s (128 GT/s)

--Diblidabliduu (talk) 21:22, 9 December 2012 (UTC)

It's explained in the article. GT/s = gigatransfers/s.

PCIe 1 & 2 use 8b/10b encoding, thus 2.5 GT/s = 250 MB/s, 5 GT/s = 500 MB/s. PCIe switched to 128b/130b encoding, so it's 8 GT/s ≈ 985 MB/s. Zac67 (talk) 21:51, 9 December 2012 (UTC)

Yeah, ok. Thanks. --Diblidabliduu (talk) 21:57, 9 December 2012 (UTC)

Picture of Edge Connectors (full size)

I think this article needs a picture of closeups of edge connectors. Preferably all sizes to complement the picture of the slots. 123.243.109.192 (talk) 03:43, 13 January 2013 (UTC)

I don't know what you mean by "edge connectors", but if you mean it needs one or more images of the actual PCIe x1 and PCEe x16 slots (like this), then I absolutely agree with you. Right now the only three pictures in the article are of MiniPCI and MiniPCI Express cards. --82.170.113.123 (talk) 17:41, 25 March 2013 (UTC)

use of SMBus at PCI Express add-in cards

On what kind of real existing PCI(e) add-in cards are SMBus-Devices implemented and with what kind of functionality is the SMBus used on this PCI(e) add-in cards? Erik--87.158.143.13 (talk) 20:24, 25 February 2013 (UTC)

PCI Express config space

Should the PCI Express config space link be removed? It is broken and essentially addressed by the PCI config space link.

Spinlock55 (talk) 17:32, 18 March 2013 (UTC)

PCIe uses the same (software) configuration mechanism as PCI, so the config space isn't much different (if any). Zac67 (talk) 20:04, 18 March 2013 (UTC)

Thanks! The config space link is less confusing now. Spinlock55 (talk) 16:12, 22 March 2013 (UTC)

copper vs fiber-optic latency

"Certain data-center applications (such as large computer clusters) require the use of fiber-optic interconnects due to the distance and latency limitations inherent in copper cabling."

'latency limitations inherent in copper cabling'

http://answers.yahoo.com/question/index?qid=20080822183553AAqkj9m http://physics.stackexchange.com/questions/2537/physically-induced-latency-in-internet-connections

These links suggest that the commonly used fiber is slower, but recently there has been development of hollow/empty core fiber which is faster, so certainly some financial trade related data centers and cables could be using it already.

http://www.nature.com/nphoton/journal/vaop/ncurrent/full/nphoton.2013.45.html