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Cortex A57/A53 MPCore big.LITTLE CPU chip

ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings, coupling relatively battery-saving and slower processor cores (LITTLE) with relatively more powerful and power-hungry ones (big). Typically, only one "side" or the other will be active at once, but all cores have access to the same memory regions, so workloads can be swapped between Big and Little cores on the fly.[1] The intention is to create a multi-core processor that can adjust better to dynamic computing needs and use less power than clock scaling alone. ARM's marketing material promises up to a 75% savings in power usage for some activities.[2] Most commonly, ARM big.LITTLE architectures are used to create a multi-processor system-on-chip (MPSoC).

In October 2011, big.LITTLE was announced along with the Cortex-A7, which was designed to be architecturally compatible with the Cortex-A15.[3] In October 2012 ARM announced the Cortex-A53 and Cortex-A57 (ARMv8-A) cores, which are also intercompatible to allow their use in a big.LITTLE chip.[4] ARM later announced the Cortex-A12 at Computex 2013 followed by the Cortex-A17 in February 2014. Both the Cortex-A12 and the Cortex-A17 can also be paired in a big.LITTLE configuration with the Cortex-A7.[5][6]

The Problem that big.LITTLE Solves[edit]

For a given library of CMOS logic, active power increases as the logic switches more per second, while leakage increases with the number of transistors. So, CPUs designed to run fast are different from CPUs designed to save power. When a very fast out-of-order CPU is loafing at very low speeds, a CPU with much less leakage (fewer transistors) could do the same work. For example, it might use a smaller (fewer transistors) memory cache, or a simpler microarchitecture such as a pipeline. big.LITTLE is a way to optimize for both cases: Power and speed, in the same system.

In practice, a big.LITTLE system can be surprisingly inflexible. One issue is the number and types of power and clock domains that the IC provides. These may not match the standard power management features offered by an operating system. Another is that the CPUs no longer have equivalent abilities, and matching the right software task to the right CPU becomes more difficult. Most of these problems are being solved by making the electronics and software more flexible.

Run-state migration[edit]

There are three ways[7] for the different processor cores to be arranged in a big.LITTLE design, depending on the scheduler implemented in the kernel.[8]

Clustered switching[edit]

Big.Little clustered switching

The clustered model approach is the first and simplest implementation, arranging the processor into identically-sized clusters of "big" or "LITTLE" cores. The operating system scheduler can only see one cluster at a time; when the load on the whole processor changes between low and high, the system transitions to the other cluster. All relevant data are then passed through the common L2 cache, the active core cluster is powered off and the other one is activated. A Cache Coherent Interconnect (CCI) is used. This model has been implemented in the Samsung Exynos 5 Octa (5410).[9]

In-kernel switcher (CPU migration)[edit]

Big.Little in-kernel switcher

CPU migration via the in-kernel switcher (IKS) involves pairing up a 'big' core with a 'LITTLE' core, with possibly many identical pairs in one chip. Each pair operates as one so-termed virtual core, and only one real core is (fully) powered up and running at a time. The 'big' core is used when the demand is high and the 'LITTLE' core is employed when demand is low. When demand on the virtual core changes (between high and low), the incoming core is powered up, running state is transferred, the outgoing is shut down, and processing continues on the new core. Switching is done via the cpufreq framework. A complete big.LITTLE IKS implementation was added in Linux 3.11. big.LITTLE IKS is an improvement of cluster migration (§ Clustered switching), the main difference being that each pair is visible to the scheduler.

A more complex arrangement involves a non-symmetric grouping of 'big' and 'LITTLE' cores. A single chip could have one or two 'big' cores and many more 'LITTLE' cores, or vice versa. Nvidia created something similar to this with the low-power 'companion core' in their Tegra 3 System-on-Chip.

Heterogeneous multi-processing (global task scheduling)[edit]

Big.Little heterogeneous multi-processing

The most powerful use model of big.LITTLE architecture is Heterogeneous Multi-Processing (HMP), which enables the use of all physical cores at the same time. Threads with high priority or computational intensity can in this case be allocated to the "big" cores while threads with less priority or less computational intensity, such as background tasks, can be performed by the "LITTLE" cores.[10][11]

This model has been implemented in the Samsung Exynos starting with the Exynos 5 Octa series (5420, 5422, 5430),[12][13] and Apple mobile application processors starting with the Apple A11.[14]


The paired arrangement allows for switching to be done transparently to the operating system using the existing dynamic voltage and frequency scaling (DVFS) facility. The existing DVFS support in the kernel (e.g. cpufreq in Linux) will simply see a list of frequencies/voltages and will switch between them as it sees fit, just like it does on the existing hardware. However, the low-end slots will activate the 'Little' core and the high-end slots will activate the 'Big' core.

Alternatively, all the cores may be exposed to the kernel scheduler, which will decide where each process/thread is executed. This will be required for the non-paired arrangement but could possibly also be used on the paired cores. It poses unique problems for the kernel scheduler, which, at least with modern commodity hardware, has been able to assume all cores in a SMP system are equal rather than heterogeneous.

Advantages of global task scheduling[edit]

  • Finer-grained control of workloads that are migrated between cores. Because the scheduler is directly migrating tasks between cores, kernel overhead is reduced and power savings can be correspondingly increased.
  • Implementation in the scheduler also makes switching decisions faster than in the cpufreq framework implemented in IKS.
  • The ability to easily support non-symmetrical clusters (e.g. with 2 Cortex-A15 cores and 4 Cortex-A7 cores).
  • The ability to use all cores simultaneously to provide improved peak performance throughput of the SoC compared to IKS.


SoC Fabrication Big cores Little cores GPU Memory interface Wireless radio technologies Availability Devices
HiSilicon K3V3 28 nm 1.8 GHz dual-core Cortex-A15 1.2 GHz dual-core Cortex-A7 Mali-T658 H2 2013
HiSilicon Kirin 920 28 nm 1.7-2.0 GHz quad-core Cortex-A15 1.3-1.6 GHz quad-core Cortex-A7 Mali-T628 MP4 LPDDR3 LTE Cat 6 Q3 2014 Huawei Honor 6
HiSilicon Kirin 950/955 16 nm 2.3-2.5 GHz quad-core ARM Cortex-A72 1.8 GHz quad-core ARM Cortex-A53 Mali-T880 MP4 LPDDR4 LTE Cat 6 Q4 2015 (Kirin 950)

Q2 2016 (Kirin 955)

Huawei Mate 8, Huawei P9, Huawei Honor 8
HiSilicon Kirin 960 16 nm 2.4 GHz quad-core ARM Cortex-A73 1.8 GHz quad-core ARM Cortex-A53 Mali-G71 MP8 LPDDR4 LTE Cat 12/13 Q4 2016 Huawei Mate 9, Huawei Mate 9 Pro, Huawei Mate 9 Porche Design, Huawei P10, Huawei P10 Plus, Honor 8 Pro, Honor V9, Honor 9
Samsung Exynos 5 Octa (5410 model)[15][16] 28 nm 1.6-1.8 GHz quad-core Cortex-A15 1.2 GHz quad-core Cortex-A7 PowerVR SGX544MP3 32-bit dual-channel 800 MHz LPDDR3 (12.8 GB/sec) Q2 2013 Exynos 5-based Samsung Galaxy S4
Samsung Exynos 5 Octa (5420 model)[17] 28 nm 1.8-2.0 GHz quad-core Cortex-A15 1.3 GHz quad-core Cortex-A7 Mali-T628 MP6 32-bit dual-channel 933 MHz LPDDR3e (14.9 GB/sec) Q4 2013 Exynos 5-based Samsung Galaxy Note 3
Samsung Exynos 5 Octa (5422 model)[13] 28 nm 2.1 GHz quad-core Cortex-A15 1.5 GHz quad-core Cortex-A7 Mali-T628 MP6 32-bit dual-channel 933 MHz LPDDR3e (14.9 GB/sec) Q2 2014 Exynos 5-based Samsung Galaxy S5, Odroid-XU3, Odroid-XU4
Samsung Exynos 5 Hexa (5260 model)[13] 28 nm 1.7 GHz dual-core Cortex-A15 1.3 GHz quad-core Cortex-A7 Mali-T624 32-bit dual-channel 800 MHz LPDDR3e (12.8 GB/sec) Q2 2014 Samsung Galaxy Note 3 Neo
Samsung Exynos 5 Octa (5430 model)[18] 20 nm 1.8 GHz quad-core Cortex-A15 1.3 GHz quad-core Cortex-A7 Mali-T628 MP6 32-bit dual-channel 1066 MHz LPDDR3e (17.0 GB/sec) LTE Cat 6 Q3 2014 Samsung Galaxy Alpha[19]
Samsung Exynos 7 Octa (5433 model)[20] 20 nm 1.9 GHz quad-core Cortex-A57 1.3 GHz quad-core Cortex-A53 Mali-T760 MP6 32-bit dual-channel 825 MHz LPDDR3e (13.2 GB/sec) LTE Cat 6 Q4 2014 Samsung Galaxy Note 4 (SM-N910C)
Samsung Exynos 7 Octa (7420 model)[21] 14 nm 2.1 GHz quad-core Cortex-A57 1.5 GHz quad-core Cortex-A53 Mali-T760 MP8 LPDDR4 LTE Cat 9 Q2 2015 Samsung Galaxy S6, Samsung Galaxy S6 Edge, Samsung Galaxy Note 5, Meizu PRO 5
Samsung Exynos 7 Octa (7580 model) 28 nm HKMG 1.5 GHz quad-core Cortex-A53 1.5 GHz quad-core Cortex-A53 Mali-T720 MP2 LPDDR3 LTE Cat 6 Q2 2015 Samsung Galaxy J7, Samsung Galaxy S5 Neo, Samsung Galaxy A5/A7 (2016)
Samsung Exynos 7 Hexa (7650 model) 28 nm HKMG 1.7 GHz dual-core Cortex-A72 1.3 GHz quad-core Cortex-A53 Mali-T820 MP3 LPDDR3 LTE Cat 6 Q1 2016
Samsung Exynos 7 Octa (7870 model) 14 nm LPP 1.7 GHz quad-core Cortex-A53 1.7 GHz quad-core Cortex-A53 Mali-T830 MP2 LPDDR3 LTE Cat 6 Q2 2016 Samsung Galaxy Tab A 10.1 (2016), Samsung Galaxy J7 (2016), Samsung Galaxy J7 Prime, Samsung Galaxy J5 (2017), Samsung Galaxy J7 (2017)
Samsung Exynos 7 Octa (7880 model) 14 nm LPP 1.9 GHz quad-core Cortex-A53 1.9 GHz quad-core Cortex-A53 Mali-T830 MP3 LPDDR3 LTE Cat 7 Q2 2016 Samsung Galaxy A5 (2017), Samsung Galaxy A7 (2017)
Samsung Exynos 7 Octa (7885 model) 14nm LPP 2.2 GHz dual-core Cortex-A73 1.6 GHz hexa-core Cortex-A53 Mali-G71 MP2 LPDDR4 Downlink: LTE Cat 12, Uplink: LTE Cat 13 Q1 2018 Samsung Galaxy A8 (2018), Samsung Galaxy A8+ (2018)
Samsung Exynos 8 Octa (8890 model) 14 nm LPP 2.6 GHz quad-core M1 1.6 GHz quad-core Cortex-A53 Mali-T880 MP12 LPDDR4 Downlink: LTE Cat 12, Uplink: LTE Cat 13 Q1 2016 Samsung Galaxy S7 (930F/FD), Samsung Galaxy S7 Edge (935F/FD), Samsung Galaxy Note 7 (N930F/FD/G)
Samsung Exynos 9 Octa (8895 model) 10 nm FinFET 2.3 GHz quad-core M1 1.7 GHz quad-core Cortex-A53 Mali-G71 MP20 LPDDR4x Downlink: LTE Cat 16, Uplink: LTE Cat 13 Q1 2017 Samsung Galaxy S8 (950F/FD), Samsung Galaxy S8+ (955F/FD), Samsung Galaxy Note 8 (N950F/FD)
Renesas Mobile MP6530[22] 28 nm 2.0 GHz dual-core Cortex-A15 1.0 GHz dual-core Cortex-A7 PowerVR SGX544 Dual-channel LPDDR3 LTE Cat 4
Allwinner A80 Octa[23] 28 nm Quad-core Cortex-A15 Quad-core Cortex-A7 PowerVR G6230 Dual-channel DDR3/DDR3L/LPDDR3 or LPDDR2[24]
MediaTek MT6595[25] 28 nm 2.2 GHz quad-core Cortex-A17 1.7 GHz quad-core Cortex-A7 PowerVR G6200 (600 MHz) 32-bit dual-channel 933 MHz LPDDR3 (14.9 GB/sec) LTE Cat 4 Q2 2014
MediaTek MT6595M 28 nm 2.0 GHz quad-core Cortex-A17 1.5 GHz quad-core Cortex-A7 PowerVR G6200 (450 MHz) 32-bit dual-channel 933 MHz LPDDR3 (14.9 GB/sec) LTE Cat 4 Q2 2014
MediaTek MT6595 Turbo 28 nm 2.5 GHz quad-core Cortex-A17 1.7 GHz quad-core Cortex-A7 PowerVR G6200 (600 MHz) 32-bit dual-channel 933 MHz LPDDR3 (14.9 GB/sec) LTE Cat 4 Q3 2014
Qualcomm Snapdragon 615/616 (MSM8939/v2)[26] 28 nm 1.5-1.7 GHz Quad-core ARM Cortex-A53 1.0-1.2 GHz Quad-core ARM Cortex-A53 Adreno 405 32-bit single-channel LPDDR3 LTE Cat 4 Q3 2014
Qualcomm Snapdragon 617 (MSM8952)[27] 28 nm 1.5 GHz Quad-core ARM Cortex-A53 1.2 GHz Quad-core ARM Cortex-A53 Adreno 405 32-bit single-channel LPDDR3 LTE Cat 7 Q4 2015 HTC One A9, Alcatel Idol 4, Moto G4
Qualcomm Snapdragon 650 (MSM8956)[28] 28 nm 1.8 GHz Dual-core ARM Cortex-A72 1.4 GHz Quad-core ARM Cortex-A53 Adreno 510 32-bit dual-channel 933 MHz LPDDR3 LTE Cat 7 Q4 2015 Xiaomi Redmi Note 3 Pro, Sony Xperia X, Sony Xperia X Compact
Qualcomm Snapdragon 652 (MSM8976)[29] 28 nm 1.8 GHz Quad-core ARM Cortex-A72 1.4 GHz Quad-core ARM Cortex-A53 Adreno 510 32-bit dual-channel 933 MHz LPDDR3 LTE Cat 7 Q4 2015 Xiaomi Mi Max, Samsung Galaxy A9/A9 Pro, HTC 10 Lifestyle, Alcatel Idol 4S, BQ Aquaris X5 Plus
Qualcomm Snapdragon 808 (MSM8992)[30] 20 nm 1.8 GHz Dual-core Cortex-A57 1.5 GHz Quad-core ARM Cortex-A53 Adreno 418 32-bit 933 MHz LPDDR3 (14.9 GB/s) LTE Cat 6/7 H1 2015 LG G4, Microsoft Lumia 950, Nexus 5X, BlackBerry Priv, LG V10
Qualcomm Snapdragon 810 (MSM8994)[31] 20 nm 2.0 GHz Quad-core Cortex-A57 1.5 GHz Quad-core ARM Cortex-A53 Adreno 430 32-bit dual-channel 1600 MHz LPDDR4 (25.6 GB/s) LTE Cat 6/7 H1 2015 Sony Xperia Z5, LG G Flex 2, OnePlus 2, Microsoft Lumia 950 XL, Nexus 6P, HTC One M9
Qualcomm Snapdragon 820/821 (MSM8996/MSM8996 Pro) 14 nm LPP 1.8–2.34 GHz Dual-core Kryo 1.36–2.19 GHz Dual-core Kryo Adreno 530 LPDDR4 Down: LTE Cat 12,

Up: LTE Cat 13

Q4 2015 LG G5, OnePlus 3/3T, V20, Samsung Galaxy S7/S7 Edge (US), Samsung Galaxy Note 7 (US), Xiaomi Mi5, Xiaomi Mi5s/Mi5s Plus, Google Pixel/Pixel XL, Moto Z, LG G6
Qualcomm Snapdragon 835 (MSM8998) 10 nm FinFET 2.35–2.45 GHz Quad-core Kryo 1.8–1.9 GHz Quad-core Kryo Adreno 540 LPDDR4x Down: LTE Cat 16,

Up: LTE Cat 13

Q4 2016 Samsung Galaxy S8 (US/China), Xiaomi Mi 6, HTC U11, Sony Xperia XZ Premium, ZTE Nubia Z17, OnePlus 5, Moto Z2 Force, Samsung Galaxy Note 8 (US/China), Nokia 8, LG V30, Asus ZenFone 4 Pro, Xperia XZ1, Xperia XZ1 Compact, Pixel 2/Pixel XL 2, Essential Phone, Razer Phone, Oculus Quest


In May 2017, ARM announced DynamIQ as the successor to big.LITTLE.[32] DynamIQ is expected to allow for more flexibility and scalability when designing multi-core processors. In contrast to big.LITTLE, it increases the maximum number of cores in a cluster to 8, allows for varying core designs within a single cluster, and up to 32 total clusters. The technology also offers more fine grained per core voltage control and faster L2 cache speeds. However, DynamIQ is incompatible with previous ARM designs and is initially only supported by the Cortex-A75 and Cortex-A55 CPU cores.


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Further reading[edit]

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