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Eby Friedman

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Eby G. Friedman
Born (1957-08-10) 10 August 1957 (age 67)
Jersey City, New Jersey
EducationLafayette College
University of California, Irvine
AwardsIEEE Fellow
IEEE CAS Charles A. Desoer Technical Achievement Award
Fulbright Scholar
University of California, Irvine Engineering Hall of Fame
Scientific career
FieldsElectrical and Computer Engineering
InstitutionsUniversity of Rochester
Technion – Israel Institute of Technology
Hughes Aircraft Company
Doctoral advisorJames H. Mulligan, Jr.
Websitewww.ece.rochester.edu/~friedman

Eby G. Friedman is a Fellow of the IEEE[1] and Distinguished Professor at the University of Rochester in the fields of integrated circuits, VLSI design and analysis, clock synchronization, power delivery, 3-D integration, and mixed-signal circuits. Professor Friedman is also a Visiting Professor at the Technion - Israel Institute of Technology.[2] Born in Jersey City, New Jersey in 1957, he received a Ph.D. degree from the University of California, Irvine in Electrical Engineering.[2] Professor Friedman is married to Laurie Friedman and they have two sons.

Academic Leadership and Service

Selected bibliography

Books

  • Clock Distribution Networks in VLSI Circuits and Systems (IEEE Press, 1995)[20]
  • High Performance Clock Distribution Networks (Kluwer Academic Publishers, 1997)[20]
  • Analog Design Issues in Digital VLSI Circuits and Systems (Kluwer Academic Publishers, 1997)[20]
  • Timing Optimization through Clock Skew Scheduling ( 2000 and 2009)(first and second edition)[20]
  • On-Chip Inductance in High Speed Integrated Circuits (Kluwer Academic Publishers, 2001)[21]
  • Power Distribution Networks in High Speed Integrated Circuits (Kluwer Academic Publishers, 2004)[22]
  • Multi-Voltage CMOS Circuit Design (John Wiley & Sons Press, 2006)[23]
  • Power Distribution Networks with On-Chip Decoupling Capacitors (Springer Verlag, 2008 and 2011)(first and second edition) [24]
  • Three-Dimensional Integrated Circuit Design (Morgan Kaufmann, 2009)[25]
  • High Performance Integrated Circuit Design (McGraw-Hill Publishers, 2012) [26]
  • J. Rosenfeld and E. G. Friedman, On-Chip Resonance in Nano scale Integrated Circuits: Design and Analysis Methodologies for Advanced Data, Clock, and Power Generation Networks[27]
  • D. Velenis and E. G. Friedman, Delay Uncertainty in High Performance Clock Distribution Networks Issues and Solutions [28]
  • M. El-Moursy and E. Friedman, On-Chip Inductive Interconnect Design Methodologies[29]
  • Professor Friedman has published almost 500 papers and is co-inventor of 13 patents in the fields of high speed and low power CMOS design techniques, interconnect and substrate noise, pipelining and retiming, three-dimensional integration, and the theory and application of power and synchronous clock distribution networks.[30]

Articles

  • I. Vaisband, B. Price, S. Kose, Y. Kolla, E. G. Friedman, and J. Fischer, " Distributed LDO Regulators in a 28 nm Power Delivery System," Analog Integrated Circuits and Signal Processing, Volume 83, Issue 3, pp. 295 – 309, 2015.[20]
  • I. Vaisband and E. G. Friedman, " Energy Efficient Clustering of On-Chip Power Delivery Systems," Integration, the VLSI Journal, Volume 48, pp. 1 – 9, 2015.[20]
  • M. Kazemi, E. Ipek, and E. G. Friedman, " Adaptive Compact Magnetic Tunnel Junction Model," IEEE Transactions on Electron Devices, Vol. 61, No. 11, pp. 3883–3891, November 2014.[20]
  • S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, " Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 10, pp. 2054–2066, October 2014.[20]
  • A. Shapiro and E. G. Friedman, " MOS Current Mode Logic Near Threshold Circuits," Journal on Low Power Electronics and Applications, Volume 4, pp. 138 – 152, 2014.[20]
  • R. Patel, E. Ipek, and E. G. Friedman, " 2T - 1R STT-MRAM Memory Cells for Enhanced Sense Margin and On/Off Current Ratio," Microelectronics Journal, Volume 45, Issue 2, pp. 133 – 143, February 2014.[20]
  • S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, " Memristor-Based Multithreading," IEEE Computer Architecture Letters, Vol. 13, No. 1, pp. 41 – 44, January–June 2014.[20]
  • Friedman, Eby G. "Clock distribution networks in synchronous digital integrated circuits." Proceedings of the IEEE 89.5 (2001): 665-692.
  • Ismail, Yehea, and Eby G. Friedman. "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 8.2 (2000): 195-206.
  • Ismail, Yehea, Eby G. Friedman, and Jose L. Neves. "Figures of merit to characterize the importance of on-chip inductance." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 7.4 (1999): 442-449.
  • Hauryla, Mikhail, et al. "On-chip optical interconnect roadmap: challenges and critical directions." Selected Topics in Quantum Electronics, IEEE Journal of12.6 (2006): 1699-1705.

References

  1. ^ "Charles A. Desoer Technical Achievement Award | IEEE Circuits and Systems Society". Ieee-cas.org. Retrieved 2015-07-14.
  2. ^ a b "Directory : Electrical and Computer Engineering". Ece.rochester.edu. Retrieved 2015-07-14.
  3. ^ "Publications search". ieee-cas.org. Retrieved 2015-07-14.
  4. ^ "Publications search". ieeexplore.ieee.org. Retrieved 2015-07-14.
  5. ^ "Publications search". Worldscientific.com. Retrieved 2015-07-14.
  6. ^ "Publications search". Springer.com. Retrieved 2015-07-14.
  7. ^ "Publications search". elsevier.com. Retrieved 2015-07-14.
  8. ^ "Publications search". aspbs.com. Retrieved 2015-07-14.
  9. ^ "Publications search" (PDF). eecs.wsu.edu. Retrieved 2015-07-14.
  10. ^ "Publications search" (PDF). nd.edu. Retrieved 2015-07-14.
  11. ^ http://www.iscas2012.org/img/main/Conference_Guide.pdf
  12. ^ "Publications search". researchgate.net. Retrieved 2015-07-14.
  13. ^ "Publications search" (PDF). ieee-cas.org. Retrieved 2015-07-14.
  14. ^ "Publications search" (PDF). springer.com. Retrieved 2015-07-14.
  15. ^ "Publications search". ieeexplore.ieee.org. Retrieved 2015-07-14.
  16. ^ "Publications search". ieeexplore.ieee.org. Retrieved 2015-07-14.
  17. ^ "Publications search". ieeexplore.ieee.org. Retrieved 2015-07-14.
  18. ^ "Publications search" (PDF). ieee-cas.org. Retrieved 2015-07-14.
  19. ^ "Publications search". ieeexplore.ieee.org. Retrieved 2015-07-14.
  20. ^ a b c d e f g h i j k Eby G. Friedman. "Clock Distribution Networks in Synchronous Digital Integrated Circuits" (PDF). Eecs.wsu.edu. Retrieved 2014-07-14.
  21. ^ "On-Chip Inductance in High-Speed Integrated Circuits" (PDF). Ece.northwestern.edu. Retrieved 2014-07-14.
  22. ^ Mikhail Popovich. "High Performance Power Distribution Networks with On-Chip Decoupling Capacitors for Nanoscale Integrated Circuits" (PDF). Ece.rochester.edu. Retrieved 2014-07-14.
  23. ^ Zhiyu Liu. "Multi-Voltage Nanoscale CMOS Circuit Techniques" (PDF). Ihome.ust.hk. Retrieved 2014-07-14.
  24. ^ Mikhail Popovich; Andrey V. Mezhiba; Selçuk Köse; Eby Friedman. "Power Distribution Networks with On-Chip Decoupling Capacitors" (PDF). Ihome.ust.hk. Retrieved 2014-07-14.
  25. ^ F. Pavlidis; Eby G. Friedman. "Three-Dimensional Integrated Circuit Design". Elsevier Inc. Retrieved 2014-07-14.
  26. ^ Emre Salman; Eby Friedman. "High Performance Integrated Circuit Design". McGraw Hill Professional. Retrieved 2014-07-14.
  27. ^ J. Rosenfeld; E. G. Friedman. "On-Chip Resonance in Nanoscale Integrated Circuits" (PDF). Lambert Academic. Retrieved 2014-07-14.
  28. ^ D. Velenis; E. G. Friedman. "Delay Uncertainty in High Performance Clock Distribution Networks: Issues and Solutions". Lambert Academic. Retrieved 2014-07-14.
  29. ^ M. El-Moursy; E. Friedman. "Delay Uncertainty in High Performance Clock Distribution Networks: Issues and Solutions". VDM Publishing,. Retrieved 2014-07-14.{{cite web}}: CS1 maint: extra punctuation (link)
  30. ^ "high speed and low power CMOS design techniques, interconnect and substrate noise, pipelining and retiming, three-dimensional integration, and the theory and application of power and synchronous clock distribution networks". Retrieved 2014-07-14.
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