CMOS

"CMOS" can also refer to nonvolatile memory of a personal computer; see Nonvolatile BIOS memory.

For the style guide sometimes called "CMOS" see The Chicago Manual of Style.

CMOS ("see-moss"), which stands for complementary metal-oxide-semiconductor, is a major class of integrated circuits. CMOS chips include microprocessor, microcontroller, static RAM, and other digital logic circuits. The central characteristic of the technology is that it only uses significant power when its transistors are switching between on and off states. Consequently, CMOS devices use little power and do not produce as much heat as other forms of logic. CMOS also allows a high density of logic functions on a chip.

The word "complementary" refers to the fact that the design uses pairs of transistors for logic functions, only one of which is switch on at any time.

The phrase "metal-oxide-semiconductor" is a reference to the nature of the fabrication process originally used to build CMOS chips. That process created field effect transistors having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Instead of metal, today the gate electrodes are almost always made from a different material, polysilicon, but the name CMOS nevertheless continues to be used for the modern descendants of the original process. (See also MOSFET.)

A chip with a large number of CMOS transistors packed tightly together is sometimes known as CHMOS (for "Complementary High-density metal-oxide-semiconductor").

Development history

CMOS circuits were invented in 1963 by Frank Wanlass at Fairchild Semiconductor. The first CMOS integrated circuits were made by RCA in 1968 by a group led by Albert Medwin. Originally a low-power but slow alternative to TTL, CMOS found early adopters in the watch industry and in other fields where battery life was more important than speed. Some twenty-five years later, CMOS has become the predominant technology in digital integrated circuits. This is essentially because area occupation, operating speed, energy efficiency and manufacturing costs have benefited and continue to benefit from the geometric downsizing that comes with every new generation of semiconductor manufacturing processes. In addition, the simplicity and comparatively low power dissipation of CMOS circuits have allowed for integration densities not possible on the basis of bipolar junction transistors.

Standard discrete CMOS logic functions were originally available only in the 4000 series of logic integrated circuits. Later many functions in the 7400 series began to be fabricated in CMOS, NMOS, BiCMOS or another variant.

Early CMOS circuits were very susceptible to damage from electrostatic discharge (ESD). Subsequent generations were thus equipped with sophisticated protection circuitry that helps absorb electric charges with no damage to the fragile gate oxides and PN-junctions. Still, antistatic handling precautions for semiconductor devices continue to be followed to prevent excessive energies from building up. Manufacturers recommend using antistatic precautions when adding a memory module to a computer, for instance.

On the other hand, early generations such as the 4000 series that used aluminum as a gate material were extremely tolerant of supply voltage variations and operated anywhere from 3 to 18 volts DC. For many years, CMOS logic was designed to operate from the then industry-standard of 5 V imposed by TTL. By 1990, lower power dissipation was usually more important than easy interfacing to TTL, and CMOS voltage supplies began to drop along with the geometric dimensions of the transistors. Lower voltage supplies not only saved power, but allowed thinner, higher performance gate insulators to be used. Some modern CMOS circuits operate from voltages below one volt.

In the early fabrication processes, the gate electrode was made of aluminum. Later CMOS processes switched to polycrystalline silicon ("polysilicon"), which can better tolerate the high temperatures used to anneal the silicon after ion implantation. This means that the gate can be put on early in the process and then used directly as an implant mask producing a self aligned gate (gates that are not self aligned require overlap which increases device size and stray capacitance). As of 2004 there is some research into using metal gates once again, but all commonly used processes have polysilicon gates. There is also a a great deal of research going on to replace the silicon dioxide gate dielectric with a high-k dielectric material to combat increasing leakage currents.

Technical details

CMOS (complementary metal oxide semiconductor) refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS logic on a CMOS process dissipates less energy and is more dense than other implementations of the same functionality. As this advantage has grown and become more important, CMOS processes and variants have come to dominate, so that as of 2006 the vast majority of integrated circuit manufacturing by dollar volume is on CMOS processes.

Structure

CMOS logic uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications and signal processing equipment. Although CMOS logic can be implemented with discrete devices (for instance, in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions (or hundreds of millions) of transistors of both types on a rectangular piece of silicon of between 0.1 and 4 square centimeters. These bits of silicon are commonly called chips, although within the industry they are also referred to as die, perhaps because they are the result of dicing (that is, cutting up) the circular silicon wafer which is the basic unit of semiconductor device fabrication.

In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network between the output and the lower-voltage power supply rail (often named V_ss). Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up network between the output and the higher-voltage rail (often named V_dd). The p-type transistor network is complementary to the n-type transistor network, so that when the n-type is off, the p-type is on, and vice-versa.

CMOS logic dissipates less power than NMOS logic because CMOS dissipates power only when switching (dynamic power). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happen once every ten nanoseconds. NMOS logic dissipates power whenever the output is low (static power), because there is a current path from V_dd to V_ss through the load resistor and the n-type network.

P-type MOSFETs are complementary to n-type because they turn on when their gate voltage goes sufficiently below their source voltage, and because they can pull the drain all the way to V_dd. Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be on when the n-type MOSFET is off, and vice-versa.

Example: NAND gate

As an example, shown on the right is a circuit diagram of a NAND gate in CMOS logic.

If both of the A and B inputs are high, then: both the n-type transistors (bottom half of the diagram) will conduct, neither of the p-type transistors (top half) will conduct, and a conductive path will be established between the output and V_ss, bringing the output low. If either of the A or B inputs is low, one of the n-type transistors will not conduct, one of the p-type transistors will, and a conductive path will be established between the output and V_dd, bringing the output high.

Another advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See Logical effort for a method of calculating delay in a CMOS circuit.

Example: NAND gate in physical layout

File:CMOS NAND Layout.png

The physical layout of a NAND circuit (based on the CMOS logic example given)

This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the NAND (illustrated in green coloring) are in polysilicon. The CMOS transistors (devices) are formed by the intersection of the polysilicon and diffusion: N diffusion for the N device; P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares. The physical layout example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate. The P devices is manufactured in an N-type well (n-well). A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent latchup.

Power: Switching and leakage

CMOS circuits dissipate power by charging and discharging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: $P=CV^{2}f$ .

A different form of power consumption became noticeable in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transistions. During the middle of these transitions, both the NMOS and PMOS networks are partially conductive, and current flows directly from V_dd to V_ss. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires has ameliorated this effect, and crowbar power is nearly always substantially smaller than switching power.

Both NMOS and PMOS transistors have a threshold gate-to-source voltage, below which the current through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (V_dd might have been 5 V, and V_th for both NMOS and PMOS might have been 700 mV). But as supply voltages have come down to conserve power the V_dd to V_ss short circuit is avoided.

However, to speed up the designs, manufacturers have switched to gate materials which lead to lower voltage thresholds and a modern NMOS transistor with a V_th of 200 mV has a significant subthreshold (see "exponentially" in paragraph above) leakage current. Designs (e.g. desktop processors) which try to optimize their fabrication processes for minimum power dissipation during operation have been lowering V_th so that leakage power begins to approximate switching power. As a result, these devices dissipate considerable power even when not switching. Leakage power reduction using new material and system design is critical to sustaining scaling of CMOS. The industry is contemplating the introduction of High-k Dielectrics to combat the increasing gate leakage current by replacing the silicon dioxide that are the conventional gate dielectrics with materials having a higher dielectric constant. A good overview of leakage and reduction methods are explained in Leakage in Nanometer CMOS Technologies ISBN 0387257373.

External links

CMOS gate description and interactive illustrations
LASI is a "general purpose" IC layout CAD tool. It is a free download and can be used as a layout tool for CMOS circuits.