IBM AP-101
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The IBM AP-101 is an avionics computer, used most notably in the U.S. Space Shuttle, and also in the B-52 and B-1B bombers,[1] among others. It is a repackaged version of the AP-1 used in the F-15 fighter.[2] When it was designed, it was a high-performance pipelined processor with core memory. While today[update] its specifications are exceeded by most of the modern microprocessors, it was considered high-performance for its era as it could process 480,000 instructions per second (compared to the 7,000 instructions per second of the computer used on Gemini spacecraft).[1] It remains in service (formerly on the space shuttle) because it works and is flight-certified, whereas a new certification would be too expensive. The Space Shuttle AP-101s were augmented by glass cockpit technology.
The AP-101, being the top-of-the-line of the System/4 Pi range, shares its general architecture with the System/360 mainframes.[1] It has 16 32-bit registers, and uses a microprogram to define an instruction set of 154 instructions. Originally only 16 bits were available for addressing memory; later this was extended with four bits from the program status word register, allowing a directly addressable memory range of 1M locations.
The original AP-101 was built using TTL integrated circuits. The main memory was originally core memory, but the AP-101S upgrade in the early 1990s used semiconductor memory.
The space shuttle used five AP-101 computers as "general-purpose computers" (GPCs). Four operate in sync, for redundancy, while the fifth is a backup running software written independently. The shuttle software was written in HAL/S, a special-purpose high-level language, whereas AP-101s used by the US Air Force are mostly programmed in JOVIAL, such as the system found on the B-1B Lancer bomber.[3]
References
Papers
- Norman, P. Glenn (1987), "The new AP101S General-Purpose Computer (GPC) for the Space Shuttle", IEEE Proceedings, 75 (3): 308–319, doi:10.1109/PROC.1987.13738
- Vandling, Gilbert C. Organization of a Microprogrammed Aerospace Computer. Computer Design, pp. 65–72, February 1975.
External links
- NASA description of shuttle GPCs
- NASA history of AP-101 development
- Space Shuttle Computers and Avionics