In electronics, a multi-level cell (MLC) is a memory element capable of storing more than a single bit of information, compared to a single-level cell (SLC) which can store only one bit per memory element.
Triple-level cells (TLC) and quad-level cells (QLC) are versions of MLC memory, which can store 3 and 4 bits per cell, respectively. Note that due to the convention, the name "multi-level cell" is sometimes used specifically to refer to the "two-level cell", which is slightly confusing. Overall, the memories are named as follows:
- SLC (1 bit per cell) - fastest, highest cost
- MLC (2 bits per cell)
- TLC (3 bits per cell)
- QLC (4 bits per cell) - slowest, least cost
Examples of MLC memories are MLC NAND flash, MLC PCM (phase change memory), etc. For example, in SLC NAND flash technology, each cell can exist in one of the two states, storing one bit of information per cell. Most MLC NAND flash memory has four possible states per cell, so it can store two bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. Multi-level cells which are designed for low error rates are sometimes called enterprise MLC (eMLC). There are tools for modeling the area/latency/energy of MLC memories.
Flash memory stores data in individual memory cells, which are made of floating-gate transistors. Traditionally, each cell had two possible states, so one bit of data was stored in each cell in so-called single-level cells, or SLC flash memory. SLC memory has the advantage of faster write speeds, lower power consumption and higher cell endurance. However, because SLC memory stores less data per cell than MLC memory, it costs more per megabyte of storage to manufacture. Due to faster transfer speeds and expected longer life, SLC flash technology is used in high-performance memory cards. At least that is the conventional view. In February 2016, a study was published that showed little difference in practice between the reliability of SLC and MLC.
The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density, and memory-reading software can compensate for a larger bit error rate. The higher error rate necessitates an error correcting code (ECC) that can correct multiple bit errors; for example, the SandForce SF-2500 Flash Controller can correct up to 55 bits per 512-byte sector with an unrecoverable read error rate of less than one sector per 1017 bits read. The most commonly used algorithm is Bose-Chaudhuri-Hocquenghem (BCH code). Other drawbacks of MLC NAND are lower write speeds, lower number of program-erase cycles and higher power consumption compared to SLC flash memory.
A few memory devices go the other direction, and use two cells per bit, to give even lower bit error rates. The Intel 8087 uses two-bits-per-cell technology, and in 1980 was one of the first devices on the market to use multi-level ROM cells. Some solid-state disks use part of a MLC NAND die as if it were single-bit SLC NAND, giving higher write speeds.
In a broad sense, each nucleotide in any living being's DNA can be regarded as a MLC (two-level) cell. Since the DNA system uses 4 types of nucleotides, each one can be viewed as being equivalent to 2 bits of data, because 2 bits can represent exactly 4 different combinations (00, 01, 10, and 11).
Samsung announced a type of NAND flash that stores three bits of information per cell, with eight total voltage states. This is commonly referred to as Triple Level Cell (TLC) and was first seen in the 840 Series SSDs. Samsung refers to this technology as 3-bit MLC. SanDisk X4 flash memory cards are based on NAND-memory that stores four bits per cell, using 16 discrete charge levels (states) in each individual transistor. The negative aspects of MLC are amplified with TLC, but TLC benefits from still higher storage density and lower cost.
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