Talk:Register-transfer level

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isn't RTL also used for asynchronous digital circuits?

Link to Resistor–transistor logic?[edit]

If RTL-level design was ever used for RTL-logic design, and we could find a source to that effect, there might be a reason to imagine a relationship. But TTL and ECL and CMOS are more likely targets for it, and they're not linked, to let's not link the Resistor–transistor logic that's related only by initialism. Same from the other side(s). Dicklyon (talk) 02:29, 24 April 2008 (UTC)

Relationship between HDL and RTL[edit]

  • Is it correct to say that HDLs allow to express a digital circuit at the abstraction of RTL?
  • RTL is used in the logic design phase of the integrated circuit design cycle.
  • When designing digital integrated circuits with a hardware description language, the designs are usually engineered at a higher level of abstraction than transistor or gate level.

Thanks, --Abdull (talk) 23:17, 8 February 2010 (UTC)

Clock edge[edit]

The article says "...changes its state on each clock edge.". Shouldn't this be "...each rising clock edge." or "...each positive clock edge"? Ellingd (talk) 16:53, 2 March 2010 (UTC)

VHDL example[edit]

D latch operation: at the edge of a clock, input will be made available at the output. The example, however implies that the input function is synchronised.

Wrong

process(clk)
begin
    if rising_edge(clk) then
        D <= not Q;
    end if;
end process;

Right

D <= not Q;

process(clk)
begin
    if rising_edge(clk) then
        Q <= D;
    end if;
end process;

--Armandas j (talk) 15:11, 15 April 2010 (UTC)

Proposed merge with State of art power estimation techniques for RTL[edit]

"Power estimation" would make a good addition to this existing RTL page, would improve the sources for this topic, and neither page is big enough that a spinoff is necessary. — {{U|Technical 13}} (etc) 14:24, 22 April 2015 (UTC)

Agreed and  Done Klbrain (talk) 21:25, 14 October 2017 (UTC)