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DRAFT - Comparison of electronic design automation tools (draft)
Company | Name | license | Last updates | process | input | output | Notes |
---|---|---|---|---|---|---|---|
Cynthesizer | commercial | Last updates | high-level synthesis (details needed) | SystemC | Verilog RTL | ||
Forte Labs | Autoesl | commercial | Last updates | http://deepchip.com/items/0482-06.html | |||
http://www.c-to-verilog.com/ | c-to-verilog | Commercial | Last updates | high-level synthesis | C | Verilog | Notes |
veripool.org | Verilator | LGPL + artistic | Last updates | tbd | Verilog | SystemC or C++ | originally from DEC |
John Bass fpgac.sourceforge.net | FpgaC | open source | Last updates | compiler | ANSI C subset | Designed for reconfigurable computing | |
Celoxica | Impulse-C | commercial | Last updates | high-level synthesis | input | output | Notes |
ChipVisions PowerOpt | Low Power HLS | ||||||
Mentor Graphics | Catapult C | commercial | Last updates | high-level synthesis | untimed ANSI C/C++, selected SystemC inputs | register transfer level (RTL) code | |
Synfora | PICO | commercial | |||||
Cebatech Inc | C2R | commercial |