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Nanoimprint lithography

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A diffractive beam splitter with three-dimensional structure created using nanoimprint lithography

Nanoimprint lithography (NIL) is a method of fabricating nanometer-scale patterns. It is a simple nanolithography process with low cost, high throughput and high resolution. It creates patterns by mechanical deformation of imprint resist and subsequent processes. The imprint resist is typically a monomer or polymer formulation that is cured by heat or UV light during the imprinting. Adhesion between the resist and the template is controlled to allow proper release.

History

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The term "nanoimprint lithography" was coined in the scientific literature in 1996, when Prof. Stephen Chou and his students published a report in Science,[1] although hot embossing (now taken as a synonym of NIL) of thermoplastics had been appearing in the patent literature for a few years already. Soon after the Science publication, many researchers developed different variations and implementations. At this point, nanoimprint lithography has been added to the International Technology Roadmap for Semiconductors (ITRS) for the 32 and 22 nm nodes.

Processes

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There are many but the most important processes are the following three:

  • thermoplastic nanoimprint lithography
  • photo nanoimprint lithography
  • resist-free direct thermal nanoimprint lithography.

Thermoplastic nanoimprint lithography

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Thermoplastic nanoimprint lithography (T-NIL) is the earliest nanoimprint lithography developed by Prof. Stephen Chou's group. In a standard T-NIL process, a thin layer of imprint resist (thermoplastic polymer) is spin-coated onto the sample substrate. Then the mold, which has predefined topological patterns, is brought into contact with the sample, and they are pressed together under certain pressure. When heated up above the glass-transition temperature of the polymer, the pattern on the mold is pressed into the softened polymer film.[1] After being cooled down, the mold is separated from the sample, and the pattern resist is left on the substrate. A pattern transfer process (reactive ion etching, normally) can be used to transfer the pattern in the resist to the underneath substrate.[1]

Alternatively, cold welding between two metal surfaces could also transfer low-dimensional nanostructured metal without heating (especially for critical sizes less than ~10 nm).[2][3] Three-dimensional structures can be fabricated by repeating this procedure. The cold-welding approach has the advantage of reducing surface contact contamination or defect due to no heating process, which is a main problem in the latest development and fabrication of organic electronic devices and novel solar cells.[4]

Photo nanoimprint lithography

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In photo nanoimprint lithography (P-NIL), a UV-curable liquid resist is applied to the sample substrate, and the mold is normally made of transparent material like fused silica or PDMS. After the mold and the substrate are pressed together, the resist is cured in UV light and becomes solid. After mold separation, a similar pattern transfer process can be used to transfer the pattern in resist onto the underneath material. The use of a UV-transparent mold is difficult in vacuum, because a vacuum chuck to hold the mold would not be possible.

Resist-free direct thermal nanoimprint lithography

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Different from the above mentioned nanoimprint methods, resist-free direct thermal nanoimprint does not require an extra etching step to transfer patterns from imprint resists to the device layer.

In a typical process, photoresist patterns are first defined using photolithography. A polydimethylsiloxane (PDMS) elastomer stamp is subsequently replica-molded from the resist patterns. Further, a single-step nanoimprint directly molds thin film materials into desired device geometries under pressure at elevated temperatures. The imprinted materials should have suitable softening characteristics in order to fill up the pattern. Amorphous semiconductors (for example, chalcogenide glass[5][6]) demonstrating high refractive index and wide transparent window are ideal materials for the imprint of optical/photonic device.

This direct imprint patterning approach offers a monolithic integration alternative with potentially improved throughput and yield, and may also enable roll-to-roll processing of devices over large substrate areas inaccessible using conventional lithographic patterning methods.[7]

In thermal nanoimprint methods the trade-off between full pattern transfer and deforming the substrate creates limitations in quality of fabrication. Few approached have created other solvent-assisted methods for direct resistless nanoimprinting processes.[8][9]

Schemes

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Full-wafer nanoimprint

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In a full-wafer nanoimprint scheme, all the patterns are contained in a single nanoimprint and transferred in a single imprint step. This allows a high throughput and uniformity. An at least 8-inch (203 mm) diameter full-wafer nanoimprint with high fidelity is possible.

To ensure the pressure and pattern uniformities of full-wafer nanoimprint processes and prolong the mold lifetime, a pressing method utilizing isotropic fluid pressure, named air-cushion press (ACP)[10] by its inventors, is developed and being used by commercial nanoimprint systems. Alternatively, roll-on technologies (e.g. roll to plate) in combination with flexible stampers (e.g. PDMS) have been demonstrated for full-wafer imprint.[11]

Step-and-repeat nanoimprint

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Nanoimprint can be performed in a way similar to the step-and-repeat optical lithography. The imprint field (die) is typically much smaller than the full-wafer nanoimprint field. The die is repeatedly imprinted to the substrate with certain step size. This scheme is good for nanoimprint mold creation.

Applications

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Nanoimprint lithography has been used to fabricate devices for electrical, optical, photonic and biological applications. For electronics devices, NIL has been used to fabricate MOSFET, O-TFT, single-electron memory. For optics and photonics, intensive study has been conducted in fabrication of subwavelength resonant grating filter, surface-enhanced Raman spectroscopy (SERS) sensor,[12] polarizers, waveplate, anti-reflective structures, integrated photonics circuit and plasmonic devices by NIL. In the context of opto-electronic devices such as LEDs and solar cells, NIL is being investigated for out- and incoupling structures.[11] Sub-10 nm nanofluidic channels had been fabricated using NIL and used in DNA stretching experiment. Currently, NIL is used to shrink the size of biomolecular sorting device an order of magnitude smaller and more efficient.

Benefits

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A diffractive lens created using nanoimprint lithography
The mold used
The resulting lens

A key benefit of nanoimprint lithography is its sheer simplicity. The single greatest cost associated with chip fabrication is the optical lithography tool used to print the circuit patterns. Optical lithography requires high-power excimer lasers and immense stacks of precision-ground lens elements to achieve nanometer-scale resolution. There is no need for complex optics or high-energy radiation sources with a nanoimprint tool. There is no need for finely tailored photoresists designed for both resolution and sensitivity at a given wavelength. The simplified requirements of the technology lead to its low cost.

Silicon master molds can be used up to a few thousands imprints, while nickel molds can last for up to ten thousand cycles.

Imprint lithography is inherently a three-dimensional patterning process. Imprint molds can be fabricated with multiple layers of topography stacked vertically. Resulting imprints replicate both layers with a single imprint step, which allows chip manufactures to reduce chip fabrication costs and improve product throughput.

As mentioned above, the imprint material does not need to be finely tuned for high resolution and sensitivity. A broader range of materials with varying properties are available for use with imprint lithography. The increased material variability gives chemists the freedom to design new functional materials rather than sacrificial etch resistant polymers.[13] A functional material may be imprinted directly to form a layer in a chip with no need for pattern transfer into underlying materials. The successful implementation of a functional imprint material would result in significant cost reductions and increased throughput by eliminating many difficult chip-fabrication processing steps.[14]

Concerns

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The key concerns for nanoimprint lithography are overlay, defects, template patterning and template wear. However, recently Kumar et al. have shown that amorphous metals (metallic glasses) can be patterned on sub-100 nm scale, which can significantly reduce the template cost.[15]

Overlay

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The current overlay 3 sigma capability is 10 nm.[16] Overlay has a better chance with step-and-scan approaches as opposed to full-wafer imprint.

Defects

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As with immersion lithography, defect control is expected to improve as the technology matures. Defects from the template with size below the post-imprint process bias can be eliminated. Other defects would require effective template cleaning and/or the use of intermediate polymer stamps. When vacuum is not used during the imprint process, air can get trapped, resulting in bubble defects.[17] This is because the imprint resist layer and the template or stamp features are not perfectly flat. There is an elevated risk when the intermediate or master stamp contains depressions (which are especially easy air traps), or when the imprint resist is dispensed as droplets just before imprinting, rather than pre-spun onto the substrate. Sufficient time must be allowed for the air to escape.[18] These effects are much less critical if flexible stamper materials are used, e.g. PDMS.[11] Another issue is adhesion between stamp and resist. High adhesion (sticking) may delaminate resist, which then stays on stamp. This effect degrades pattern, reduces yield and damages stamp. It can be mitigated by employing an FDTS antistiction layer on a stamp.

Template patterning

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High resolution template patterning can currently be performed by electron beam lithography or focused ion beam patterning; however at the smallest resolution, the throughput is very slow. As a result, optical patterning tools will be more helpful if they have sufficient resolution. Such an approach has been successfully demonstrated by Greener et al. whereby robust templates were rapidly fabricated by optical patterning of a photoresist-coated metal substrate through a photomask.[19] If homogeneous patterns on large areas are required, interference lithography is a very attractive patterning technique.[20][21] Other patterning techniques (including even double patterning) may also be used. Kumar and Schroers at Yale developed the nanopatterning of amorphous metals which can be used as inexpensive templates for nanoimprinting. Currently, state-of-the-art nanoimprint lithography can be used for patterns down to 20 nm and below.[22]

Template wear

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The use of substantial pressure to not only contact but also penetrate a layer during imprinting accelerates the wear of imprint templates compared to other types of lithographic masks. Template wear is reduced with proper use of an anti-adhesion FDTS monolayer coating on a stamp. A very efficient and precise AFM based method for characterizing the degradation of PDMS stamps enables to optimize materials and processes in order to minimize wear.[23]

Other

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Future applications of nanoimprint lithography may involve the use of porous low-κ materials. These materials are not stiff and, as part of the substrate, are readily damaged mechanically by the pressure of the imprint process.

Removal of residual layers

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A key characteristic of nanoimprint lithography (except for electrochemical nanoimprinting) is the residual layer following the imprint process. It is preferable to have thick enough residual layers to support alignment and throughput and low defects.[24] However, this renders the nanoimprint lithography step less critical for critical dimension (CD) control than the etch step used to remove the residual layer. Hence, it is important to consider the residual layer removal an integrated part of the overall nanoimprint patterning process.[25][26] In a sense, the residual layer etch is similar to the develop process in conventional lithography. It has been proposed to combine photolithography and nanoimprint lithography techniques in one step in order to eliminate the residual layer.[27]

Proximity effects

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Nanoimprint proximity effect. Top: Array of depressions is more quickly filled at the edge than the center, resulting in less imprinting at the center of the array. Bottom: The wide space between two groups of protrusions tends to be filled slower than the narrow spaces between the protrusions, resulting in the formation of holes in the unpatterned area.

Nanoimprint lithography relies on displacing polymer. This could lead to systematic effects over long distances. For example, a large, dense array of protrusions will displace significantly more polymer than an isolated protrusion. Depending on the distance of this isolated protrusion from the array, the isolated feature may not imprint correctly due to polymer displacement and thickening. Resist holes can form in between groups of protrusions.[28] Likewise, wider depressions in the template do not fill up with as much polymer as narrower depressions, resulting in misshapen wide lines. In addition, a depression at the edge of a large array fills up much earlier than one located in the center of the array, resulting in within-array uniformity issues.

3D-patterning

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A unique benefit of nanoimprint lithography is the ability to pattern 3D structures, such as damascene interconnects and T-gates, in fewer steps than required for conventional lithography. This is achieved by building the T-shape into the protrusion on the template.[29] Similarly, nanoimprint lithography can be used to replicate 3D structures created using Focused Ion Beam. Although the area that can be patterned using Focused Ion Beam is limited, it can be used, for example to imprint structures on the edge of optical fibers.[30]

High aspect ratio nanostructuring

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High-aspect-ratio and hierarchically nanostructured surfaces can be cumbersome to fabricate and suffer from structural collapse. Using UV-NIL of off-stoichiometric thiol–ene-epoxy polymer it is possible to fabricate robust, large-area, and high-aspect-ratio nanostructures as well as complex hierarchically layered structures with limited collapse and defectivity.[31]

Alternative approaches

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Electrochemical nanoimprinting

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Electrochemical nanoimprinting can be achieved using a stamp made from a superionic conductor such as silver sulfide.[32] When the stamp is contacted with metal, electrochemical etching can be carried out with an applied voltage. The electrochemical reaction generates metal ions which move from the original film into the stamp. Eventually all the metal is removed and the complementary stamp pattern is transferred to the remaining metal.

Laser assisted direct imprint

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Laser assisted direct imprint (LADI)[33] is a rapid technique for patterning nanostructures in solid substrates and it does not require etching. A single or multiple excimer laser pulses melt a thin surface layer of substrate material, and a mold is embossed into the resulting liquid layer. A variety of structures with resolution better than 10 nm have been imprinted into silicon using LADI, and the embossing time is less than 250 ns. The high resolution and speed of LADI, attributed to molten silicon's low viscosity (one-third that of water), could open up a variety of applications and be extended to other materials and processing techniques.

Ultrafast nanoimprint

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Ultrafast Nanoimprint Lithography[34] or Pulsed-NIL is a technique based on the use of stamps with an heating layer integrated beneath the nanopatterned surface. Injecting a single, short (<100 μs), intense current pulse into the heating layer causes the surface temperature of the stamp to raise suddenly by several hundreds degrees °C. This results in the melting of the thermoplastic resist film pressed against it and the swift indentation of the nanostructures. In addition to the high throughput, this fast process has other advantages, namely, the fact that it can be straightforwardly scaled up to large surfaces, and reduces the energy spent in the thermal cycle with respect to the standard thermal NIL. This approach is currently pursued by ThunderNIL srl.[35]

Roller nanoimprint

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Roller processes are very well suited for large substrates (full wafer), and large scale production since they can be implemented into production lines. If used with a soft stamper, the process (imprint as well as demoulding) can be extremely soft and tolerant to surface roughness or defects. So the processing even of extremely thin and brittle substrates is possible. Imprints of silicon wafers down to a thickness of 50 μm have been demonstrated using this process.[11] For UV-Roller-NIL on opaque substrates, the UV light must flash through the flexible stamper, e.g. by integrating UV-LEDs into a quartz glass drum.

The future of nanoimprint

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Nanoimprint lithography is a simple pattern transfer process that is neither limited by diffraction nor scattering effects nor secondary electrons, and does not require any sophisticated radiation chemistry. It is also a potentially simple and inexpensive technique. However, a lingering barrier to nanometer-scale patterning is the current reliance on other lithography techniques to generate the template. It is possible that self-assembled structures will provide the ultimate solution for templates of periodic patterns at scales of 10 nm and less.[36] It is also possible to resolve the template generation issue by using a programmable template[37] in a scheme based on double patterning.

As of October 2007, Toshiba is the only company to have validated nanoimprint lithography for 22 nm and beyond.[38] What is more significant is that nanoimprint lithography was the first sub-30 nm lithography to be validated by an industrial user.

References

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  38. ^ M. LaPedus, "Toshiba claims to 'validate' nanoimprint litho," EETimes, October 16, 2007.
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