Blackfin

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This article is about the DSP microprocessor. For other uses, see Blackfin (disambiguation).
Blackfin
Designer Analog Devices
Bits 32-bit
Introduced 2000
Design RISC
Endianness Little
Registers
8 32-bit registers
Blackfin
Blackfin-processor-logo.png
ADI Blackfin Logo
Produced From 2008 to Present
Marketed by Analog Devices
Designed by Analog Devices
Common manufacturer(s)

The Blackfin is a family of 16- or 32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality supplied by 16-bit Multiply–accumulates (MACs), accompanied on-chip by a small microcontroller.[1] It was designed for a low-power, unified processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.[2][3] There are several hardware development kits for the Blackfin. Open-source operating systems for the Blackfin include uClinux.

Architecture details[edit]

Blackfin processors use a 32-bit RISC microcontroller programming model on a SIMD architecture, which was co-developed by Intel and Analog Devices, as MSA (Micro Signal Architecture).

The architecture was announced in December 2000, and first demonstrated at the Embedded Systems Conference in June, 2001.

It incorporates aspects of ADI's older SHARC architecture and Intel's XScale architecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination was designed to improve performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses various CPU models, each targeting particular applications. [4]

Architecture features[edit]

Core features[edit]

mounted Blackfin BF535

What is regarded as the Blackfin "core" is contextually dependent. For some applications, the DSP is central. It combines two 16-bit hardware MACs, two 40-bit ALUs, and a 40-bit barrel shifter. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the compiler and/or programmer. Two nested zero-overhead loops and four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions. Other applications utilize the RISC core, which includes memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

The ISA is designed for a high level of expressiveness, allowing the assembly programmer (or compiler) to optimize an algorithm for the hardware features present.

Memory and DMA[edit]

The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers reside in this 32-bit address space, so that from a programming point of view, the Blackfin has a Von Neumann architecture.

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard architecture. Instruction memory and data memory are independent and connect to the core via dedicated memory buses, designed for higher sustained data rates between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache independently.

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR flash, NAND flash and SRAM. Some Blackfin processors also include mass-storage interfaces such as ATAPI and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.

Coupled with the core and memory system is a DMA engine that can operate between any of its peripherals and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which designed for higher throughput for applications that can utilise it, such as real-time standard-definition (D1) video encoding and decoding.

Microcontroller features[edit]

The architecture contains the usual CPU, memory, and I/O found on microprocessors or microcontrollers. These features enable operating systems.

  • Memory Protection Unit: All Blackfin processors contain a Memory Protection Unit(MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin to support operating systems, RTOSs and kernels like ThreadX, µC/OS-II, or (noMMU) Linux. The Blackfin MPU does not provide address translation like a traditional Memory Management Unit (MMU), so it does not support virtual memory or separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such as WinCE or QNX. In in most of the Blackfin documentation, the MPU is referred to as a MMU.
  • User/Supervisor Modes: Blackfin supports three run-time modes: supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc.) an exception will be thrown and the kernel will then be able to shut down the offending thread/process. The official guidance from ADI on how to use the Blackfin in non-OS environments is to reserve the lowest-priority interrupt for general-purpose code so that all software is run in supervisor space.
  • Variable-Length, RISC-Like Instruction Set: Blackfin supports 16, 32 and 64-bit instructions. Commonly used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32 and 64-bit opcodes. This variable length opcode encoding is designed for code density equivalence to modern microprocessor architectures.

Media-processing features[edit]

The Blackfin instruction set contains media-processing extensions to help accelerate pixel-processing operations commonly used in video compression and image compression and decompression algorithms.

Peripherals[edit]

Blackfin processors contain an array of connectivity peripherals:

  • ATAPI
  • CAN : A wide-area, low-speed serial bus used in some automotive and industrial electronics
  • DMA with support for memory-to-memory DMA and peripheral DMA
  • EMAC (Ethernet Media Access Controller)
  • I²C (also known as TWI (two-wire interface)) : a lower speed, shared serial bus
  • MXVR : a MOST (Media Oriented Systems Transport) Network Interface Controller
  • PPI (Parallel Peripheral Interface) : A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices. The PPI can run up to 75 MHz and can be configured from 8 to 16-bits wide.
  • PWM and timers/counters
  • Real time clock
  • SPI : a fast serial bus used in some high-speed embedded electronics applications
  • SPORT : A synchronous, high speed serial port that can support TDM, I2S and a number of other configurable framing modes for connection to ADCs, DACs, other processors, FPGAs, etc.
  • UART (Universal Asynchronous Receiver Transmitter) : allows for bi-directional communication with RS232 devices (PCs, modems, PC peripherals, etc.), MIDI devices, IRDA devices
  • USB 2.0 OTG (On-The-Go)
  • Watchdog timer

All of the peripheral control registers are memory-mapped in the normal address space.

Development tools[edit]

Blackfin BF537 EZ-Kit-Lite evaluation platform

ADI provides its own software development toolchains, the original VisualDSP++ IDE and the newer CrossCore Embedded Studio (based on Eclipse CDT). Other options include Green Hills Software's MULTI IDE, the GNU GCC Toolchain for the Blackfin processor family, the OpenEmbedded project, National Instruments' LabVIEW Embedded Module, or Microsoft Visual Studio through use of AxiomFount's AxiDotNet software.

Supported operating systems, RTOSs and kernels[edit]

Blackfin supports several commercial and open-source operating systems.

OS/RTOS/Kernels on Blackfin
Title License Comments
Linux kernel GNU General Public License Integrated into mainline kernel, distributed as part of the μClinux
ThreadX Proprietary
Nucleus Proprietary
Fusion RTOS Proprietary
µC/OS-II Proprietary
velOSity Microkernel Proprietary
INTEGRITY Proprietary
RTEMS GNU General Public License
RTXC Quadros Proprietary
T2 SDE GNU General Public License
VDK Proprietary ADI's real-time kernel. Ships with VisualDSP++.
TOPPERS/JSP GNU General Public License
scmRTOS MIT License Single-Chip Microcontroller Real-Time Operating System"
.NET Micro Framework Apache License 2.0 Stand-alone version from Microsoft. Integrated version from AxiomFount.
SCIOPTA Proprietary Certified according IEC61508 for functional safety.

See also[edit]

External links[edit]

References[edit]

  1. ^ "Blackfin processor architecture overview". Retrieved 2011-04-09. 
  2. ^ "H.264 BP/MP Encoder". Analog Devices. Retrieved 2014-9-3.  Check date values in: |accessdate= (help)
  3. ^ "H.264 BP/MP Decoder Library". Analog Devices. Retrieved 2014-9-3.  Check date values in: |accessdate= (help)
  4. ^ list of products