The VAX 8600, code-named "Venus", introduced in October 1984, was the successor of the VAX-11/785. It was originally to be named "VAX-11/790", but was renamed before launch. The VAX 8600 was a successful model and at the time was the best selling high-end VAX. It was succeeded by the VAX 8800 family in 1987.
The VAX 8600 had a CPU with an 80 ns cycle time (12.5 MHz) implemented with emitter coupled logic (ECL) macrocell arrays (MCAs). The CPU consisted of four major logical sections, the E Box, F Box, I Box and M Box. The E Box executed all instructions, including floating-point instructions through microcode. It had an arithmetic logic unit (ALU) and barrel shifter. The F Box, or floating point accelerator (FPA), was an optional feature that accelerated floating-point instructions as well as integer multiplication and division. It was a two-module set consisting of an adder module and multiplier module. The adder module contained 24 macrocell arrays while the multiplier module contained 21. The I Box fetched and decoded instructions. The M Box controlled the memory and I/O, translated virtual addresses to physical addresses and contained a 16 KB data cache.
The CPU used 145 MCAs. These were large scale integration devices fabricated by Motorola in their 3 µm MOSAIC bipolar process. They were packaged in 68-pin leadless chip carriers or pin grid arrays and were mounted onto the printed circuit board in sockets or were soldered in place. An additional 1,100 small scale integration (SSI) and medium scale integration (MSI) ECL logic devices were used. These ICs were spread out over 17 modules plugged into a backplane.
The VAX 8600 supported 4 to 256 MB of ECC memory and had eight slots on the backplane for memory modules. The system originally used 4 MB memory modules populated by 32 KB metal oxide semiconductor (MOS) RAMs, which limited capacity to 32 MB. Modules with larger capacities were introduced later. The memory was controlled by the M Box, which also provided the memory array bus used to access the memory. This dedicated bus, which had an 80 ns (12.5 MHz) cycle time, contributed to the improved performance the VAX 8600 had over the VAX-11/780, which accessed memory via the Synchronous Backplane Interconnect (SBI) that was shared with I/O devices.
I/O was provided by the SBI. The VAX 8600 featured one SBI but could be configured with two. The SBIs were provided by SBI adapters that interfaced the SBI to an internal adapter bus connected to the M Box. Each SBI had 16 slots for I/O devices, although only 15 were usable as one slot was reserved for the SBI adapter. With one SBI, that SBI had a bandwidth of 13.3 MB/s. With two SBIs, they had a total bandwidth of 17.1 MB/s. The adapter bus that interfaced the SBIs to the M Box had a bandwidth of 33.3 MB/s. Unibus and Massbus were also supported, provided by adapters that plugged into the SBI. The VAX 8600 I/O cabinet contained a PDP-11 computer serving as the console, a Unibus card cage and provisions for mounting disk drives.
The VAX 8650, code-named "Morningstar", was a faster version of the VAX 8600 introduced on 4 December 1985. It was originally to be named "VAX-11/795", but was renamed before launch. The VAX 8600 was the last VAX to be 100% compatible with the VAX-11/780 and VAX-11/785, to have the PDP-11 compatibility mode, and to use the SBI also used by the VAX-11/78x. The CPU had a 55 ns cycle time (18.18 MHz).
VAX 8200 and VAX 8300
The VAX 8200 and VAX 8300, code named "Scorpio", were mid-range minicomputers introduced on 29 January 1986. The VAX 8300 was a dual-processor variant of the VAX 8200 and, with the VAX 8800 introduced on the same date, was among the first multiprocessor VAX computers. They used the KA820 CPU module containing a V-11 microprocessor operating at 5 MHz (200 ns cycle) and supported a maximum of 128 MB of ECC memory. It had one VAXBI bus and support for an optional Unibus.
VAX 8250 and VAX 8350
The VAX 8250 and VAX 8350 were faster models of the VAX 8200 and VAX 8300 introduced in early March 1987. They used the KA825 CPU module containing a V-11 microprocessor operating at 6.25 MHz (160 ns cycle).
VAX 8800 Family
Code-named "Nautilus", this was the high-end model in the VAX 8800 family. It featured two CPUs and two VAXBI buses as standard. Development of the VAX 8800 began in August–November 1982 and it was introduced on 29 January 1986. When "Polarstar" systems and a new naming convention were introduced, the VAX 8800 was renamed to VAX 8820N to distinguish it from the VAX 8820 "Polarstar". After the name adjustments and upgrading to full SMP capability, the former VAX 8700 and VAX 8800 models became VAX 88x0 machines, where "x" represented the number of CPUs, i.e. VAX 8810, 8820, 8830 and 8840. The upgrade kit included replacement numbers affixed to the front of the machine to reflect the new designation.
The VAX 8700, code-named "Nautilus", was introduced in early August 1986. It was similar to the VAX 8800, but with only one CPU and VAXBI bus. It was upgradable to a VAX 8800. It became a VAX 8810 after the SMP upgrade and revised naming convention.
The VAX 8550, code-named "Skipjack", was introduced in early August 1986. It was similar to the VAX 8700, but was not upgradable to the VAX 8800.
The VAX 8500, code-named "Flounder", was a lower-performance variant of the VAX 8550, with microcode used to insert nops during operation to limit performance.
The VAX 8530, code-named "Skipjack", was an upgraded VAX 8500 with the nops removed for improved performance. It was introduced in early March 1987.
Polarstar was a variant of Nautilus with one to four processors and an updated console processor. Models included the:
- VAX 8810 - A single processor system
- VAX 8820 - A two processor system
- VAX 8842 - A cluster of two VAX 8820 systems
- VAX 8830 - A three processor system
- VAX 8840 - A four processor system
The VAX 8800 family was based on the NMI bus, which connected the CPU, memory controller and I/O adapters. The NMI bus was a 32-bit synchronous bus with a usable bandwidth of 64 MB/s.
The VAX 8800 family central processing unit (CPU) operated at 22.22 MHz (45 ns cycle time) and was implemented with discrete emitter-coupled logic (ECL) devices spread over eight modules. The majority of the ECL devices were macrocell arrays with 1,200 logic gates, while the general-purpose registers and floating-point units were custom logic devices developed by Digital. The CPU had 64 KB of cache implemented with 10 ns and 15 ns ECL random access memory devices.
The VAX 8800 and 8700 supported one to eight memory array modules; the VAX 8550 and 8500, one to five. The memory array modules were installed in a dedicated backplane separate from the NMI backplane. The VAX 8800 and VAX 8700 supported 4 to 32 MB of memory, the VAX 8500 and VAX 8550 4 to 20 MB, using the 4 MB memory module. When the 16 MB memory module was introduced, the memory capacity of the VAX 8800 and 8700 was increased to 128 MB, and that of the VAX 8550 and 8500 to 80 MB.
The memory system consisted of three major parts, a memory controller, a transistor-transistor logic (TTL) bus and one to eight memory array modules. The memory controller was implemented with ECL gate arrays and resided on a NMI bus module. It implemented a TTL bus to which memory array modules were connected. Two memory modules were available for the VAX 8800: a 4 MB module and a 16 MB module. The 4 MB array module was an eight-layer printed circuit board populated by metal oxide semiconductor (MOS) dynamic random access memory (DRAM) devices and medium-scale integration (MSI) FAST transistor-transistor logic (TTL) devices in roughly equal numbers. The 16 MB array module was similar to the 4 MB module, but contained eight surface-mounted daughter boards, each containing 2 MB of memory built from DRAMs.
The VAX 8800 used the VAXBI bus for input/output. The VAX 8800 supported up to four VAXBI buses, with each bus supporting up to 16 I/O devices. The VAXBI bus was interfaced to the NMI bus by a NBI adapter containing a chip implementing the VAXBI bus protocol. The NBI adapter handled all CPU references and direct memory access (DMA) transactions to and from the I/O devices. The adapter operated at 5 MHz and asynchronously to the CPU as it generated its own clock signal. The NBI adapter consisted of two modules, the NBIA and NBIB. The NBIA was the NMI side of the adapter, and the NBIB the VAXBI side.
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