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Have nothing against Mediatek, but MTK6592 is not "big.LITTLE" but SMP only? What has "little.LITTLE" to do with "Heterogeneos multi-processing"? Unsourced. Was going to fix typo: implent->implment. "for the public" redundant?
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Revision as of 05:37, 19 March 2014

ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings coupling (relatively) slower, low-power processor cores with (relatively) more powerful and power-hungry ones. The intention being to create a multi-core processor that can adjust better to dynamic computing needs and use less power than clock scaling alone. In October 2011, big.LITTLE was announced along with the Cortex-A7, which was designed to be architecturally compatible with the Cortex-A15.[1] In October 2012 ARM announced the Cortex-A53 and Cortex-A57 (ARMv8-A) cores, which are also compatible with each other to allow their use in a big.LITTLE chip.[2]

Cluster migration

There are three ways[3] for the different processor cores to be arranged in a big.LITTLE design, depending on the scheduler implemented in the Linux kernel.[4] The clustered model approach is the first and simplest implementation. With this approach the operating system scheduler can only see one of the two processor clusters, when the load on one cluster hits a certain point, the system transitions to the other cluster. All relevant data is passed through the common L2 cache, the first core cluster is powered off and the other one is activated. A Cache Coherent Interconnect (CCI) is used. This model has been implemented in the Samsung Exynos 5 Octa (5410)[5]

In-kernel switcher (CPU migration)

big.LITTLE IKS

CPU migration via the in-kernel switcher (IKS) involves pairing up a 'big' core with a 'LITTLE' core, with possibly many identical pairs in one chip. Each pair operates as one virtual core, and only one real core is (fully) powered up and running at a time. The 'big' core is used when demand is high, the 'LITTLE' core when demand is low. When demand on the virtual core changes (between high and low), the incoming core is powered up, running state is transferred, the outgoing is shut down, and processing continues on the new core. Switching is done via the cpufreq framework. A complete big.LITTLE IKS implementation is expected in Linux 3.11 or 3.12. big.LITTLE IKS is an improvement of Cluster Migration, the main difference is that each pair is visible to the scheduler.

The more complex arrangement involves a non-symmetric grouping of 'big' and 'LITTLE' cores. A single chip could have one or two 'big' cores and many more 'LITTLE' cores, or vice-versa. Nvidia created something similar to this with the low-power 'companion core' in their Tegra 3 SoC.

Heterogeneous multi-processing (global task scheduling)

big.LITTLE MP

The most powerful use model of big.LITTLE is heterogeneous multi-processing (MP), which enables the use of all physical cores at the same time. Threads with high priority or computational intensity can in this case be allocated to the 'big' cores while threads with less priority or less computational intensity, such as background tasks, can be performed by the 'LITTLE' cores.[6] Upstream big.LITTLE GTS patches are expected to be fully incorporated into the mainline Linux kernel in a few quarters. This model has been implemented in the Samsung Exynos 5 Octa (5420, 5422) and Hexa (5260).[7][8]

Scheduling

The paired arrangement allows for switching to be done transparently to the operating system using the existing dynamic voltage and frequency switching (DVFS) facility. The existing DVFS support in the kernel (e.g. cpufreq in Linux) will simply see a list of frequencies/voltages and will switch between them as it sees fit, just like it does on existing hardware. However, the low-end slots will activate the 'LITTLE' core and the high-end slots will activate the 'big' core.

Alternatively, all cores may be exposed to the kernel scheduler, which will decide where each process/thread is executed. This will be required for the non-paired arrangement but could possibly also be used on paired cores. It poses unique problems for the kernel scheduler, which, at least with modern commodity hardware, has been able to assume all cores in a SMP system are equal.

Advantages of global task scheduling

  • Finer-grained control of workloads that are migrated between cores. Because the scheduler is directly migrating tasks between cores, kernel overhead is reduced and power savings can be correspondingly increased.
  • Implementation in the scheduler also makes switching decisions faster than in the cpufreq framework implemented in IKS.
  • The ability to easily support non-symmetrical SoCs (e.g. with 2 Cortex-A15 cores and 4 Cortex-A7 cores).
  • The ability to use all cores simultaneously to provide improved peak performance throughput of the SoC compared to IKS.

Implementations

SoC Semiconductor technology big cores LITTLE cores GPU Memory interface Wireless radio technologies Availability Devices
HiSilicon K3V3 28 nm 1.8 GHz dual-core Cortex-A15 1.2 GHz dual-core Cortex-A7 Mali-T658 H2 2013
Samsung Exynos 5 Octa (5410 model)[9][10] 28 nm 1.6-1.8 GHz quad-core Cortex-A15 1.2 GHz quad-core Cortex-A7 PowerVR SGX544MP3 32-bit dual-channel 800 MHz LPDDR3 (12.8 GB/sec) Q2 2013 Exynos 5-based Samsung Galaxy S4
Samsung Exynos 5 Octa (5420 model)[11] 28 nm 1.8-2.0 GHz quad-core Cortex-A15 1.3 GHz quad-core Cortex-A7 Mali-T628MP6 32-bit dual-channel 933 MHz LPDDR3e (14.9 GB/sec) Q4 2013 Exynos 5-based Samsung Galaxy Note 3
Samsung Exynos 5 Octa (5422 model)[8] 28 nm 2.1 GHz quad-core Cortex-A15 1.5 GHz quad-core Cortex-A7 Mali-T628MP6 32-bit dual-channel 933 MHz LPDDR3e (14.9 GB/sec) Q2 2014 Exynos 5-based Samsung Galaxy S5
Samsung Exynos 5 Hexa (5260 model)[8] 28 nm 1.7 GHz dual-core Cortex-A15 1.3 GHz quad-core Cortex-A7 Mali-T624 32-bit dual-channel 800 MHz LPDDR3e (12.8 GB/sec) Q2 2014 Samsung Galaxy Note 3 Neo
Renesas Mobile MP6530[12] 28 nm 2 GHz dual-core Cortex-A15 1 GHz dual-core Cortex-A7 PowerVR SGX544 Dual-channel LPDDR3 LTE CAT4
Allwinner A80 Octa[13] 28 nm Quad-core Cortex-A15 Dual-core Cortex-A7 PowerVR G6230

References

  1. ^ "ARM Unveils its Most Energy Efficient Application Processor Ever; Redefines Traditional Power And Performance Relationship With big.LITTLE Processing" (Press release). ARM Holdings. 19 October 2011. Retrieved 31 October 2012.
  2. ^ "ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors" (Press release). ARM Holdings. Retrieved 31 October 2012.
  3. ^ Brian Jeff (18 June 2013). "Ten Things to Know About big.LITTLE". ARM Holdings. Retrieved 17 September 2013.
  4. ^ George Grey (10 July 2013). "big.LITTLE Software Update". Linaro. Retrieved 17 September 2013.
  5. ^ Peter Clarke (6 August 2013). "Benchmarking ARM's big-little architecture". Retrieved 17 September 2013.
  6. ^ Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7 (PDF), ARM Holdings, September 2013, retrieved 17 September 2013
  7. ^ Brian Klug (11 September 2013). "Samsung Announces big.LITTLE MP Support in Exynos 5420". AnandTech. Retrieved 16 September 2013.
  8. ^ a b c "Samsung Unveils New Products from its System LSI Business at Mobile World Congress". Samsung Tomorrow. Retrieved 26 February 2013.
  9. ^ Andrew Cunningham (10 January 2013). "Samsung's new eight-core Exynos 5 Octa SoC promises not to hog battery". Ars Technica. Retrieved 10 January 2013.
  10. ^ James Trew (9 January 2013). "Samsung announces eight-core Exynos 5 'Octa' chip at CES". Engadget. Retrieved 10 January 2013.
  11. ^ "Samsung Primes Exynos 5 Octa for ARM big.LITTLE Technology with Heterogeneous Multi-Processing Capability" (Press release). Samsung Electronics. 10 September 2013. Retrieved 17 September 2013.
  12. ^ MP6530 (PDF), Renesas Mobile, December 2012, retrieved 17 September 2013
  13. ^ "Allwinner UltraOcta A80 processor packs a PowerVR Series6 GPU with 64 cores". Imagination. March 2014.
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