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==Namco Pole Position specifications==
==Namco Pole Position specifications==
*Main [[Central processing unit|CPU]]: [[Zilog Z80]], 3.072 [[Megahertz|MHz]]<ref>{{cite book
*Main [[Central processing unit|CPU]]: [[Zilog Z80]] @ 3.072 [[Megahertz|MHz]]<ref name=manual>{{cite book
|title=Pole Position Operation, Maintenance, and Service Manual
|title=Pole Position Operation, Maintenance, and Service Manual
|url=http://www.arcade-museum.com/manuals-videogames/P/polepos.pdf
|url=http://www.arcade-museum.com/manuals-videogames/P/polepos.pdf#page=92
|format=pdf
|format=pdf
|accessdate=2014-02-03
|accessdate=2014-02-03
Line 12: Line 12:
|publisher=[[Atari, Inc]].
|publisher=[[Atari, Inc]].
|location=[[Milpitas, California]]
|location=[[Milpitas, California]]
|pages=93–104
|pages=92–104
|chapter=Schematic Package Supplement
|chapter=Schematic Package Supplement
}}</ref> ([[8-bit|8]]/[[16-bit]] [[Instruction set|instructions]] @ 445,440 [[instructions per second]])<ref name=retro>http://www.drolez.com/retro/</ref>
}}</ref>
*Secondary CPU: 2× [[Zilog Z8000|Zilog Z8002]] @ 3.072 MHz<ref name=mame>http://mamedev.org/source/src/mame/drivers/polepos.c.html</ref> (16/[[32-bit]] instructions @ 890,880 instructions per second)<ref name=retro/>
*Secondary CPUs: 2x Zilog Z8002s, 3.072 MHz
*[[Sound chip]]: Namco six-channel [[Stereophonic sound|stereo]] [[Programmable sound generator|PSG]]; it uses one of the secondary CPUs for the sound as well.
*[[Sound chip]]: Namco six-channel [[Stereophonic sound|stereo]] [[Programmable sound generator|PSG]]; it uses one of the secondary CPUs for the sound as well.
*[[Microcontroller|MCU]]: 3× [[Fujitsu]] MB8841 & Fujitsu MB8842<ref name=mame/>
*Other [[computer chip|chip]]s: Two custom input/output controllers (type 1) handle the games' controls and [[speech synthesis|speech]].
*Other [[computer chip|chip]]s: Two custom input/output controllers (type 1) handle the games' controls and [[speech synthesis|speech]].
*[[Random-access memory|RAM]] (random-access memory)<ref name=manual/>
*[[Video resolution]]: 256 x 224
**CPU 1-2: 8 [[Kibibyte|KB]] [[video memory]]
**CPU 3: 24.625 KB (2 KB battery back-up RAM, 1 KB sound memory, 21.625 KB video memory)
*[[Read-only memory|ROM]] (read-only memory)<ref name=manual/>
**CPU 1-2: 240 KB
**CPU 3: 16 KB
*[[Video resolution]]: 256×224 to 384×264 [[pixel]]s<ref name=mame/>
*[[Color depth]]: 3840 colors<ref name=mame/>
*Graphical planes: 2 [[Tile engine|tilemap]] layers (1 background, 1 text), 1 road layer<ref name=mame/>
*[[Sprite (computer graphics)|Sprite]] capabilities: [[Framebuffer|Buffered]] sprites, sprite zooming & flipping,<ref>http://web.archive.org/web/20130104201547/http://mamedev.org/source/src/mame/video/polepos.c.html</ref>


==List of Namco Pole Position arcade games==
==List of Namco Pole Position arcade games==

Revision as of 11:25, 19 September 2014

The Namco Pole Position was an 8-bit arcade system board, which was first used by Namco in 1982 for the Pole Position arcade games; it was the first system board from the company that utilized stereophonic sound, and used NVRAM to save its high scores after a machine was turned off.

Namco Pole Position specifications

List of Namco Pole Position arcade games

References

  1. ^ a b c "Schematic Package Supplement". Pole Position Operation, Maintenance, and Service Manual (pdf). Milpitas, California: Atari, Inc. 1982. pp. 92–104. Retrieved 2014-02-03.
  2. ^ a b http://www.drolez.com/retro/
  3. ^ a b c d e http://mamedev.org/source/src/mame/drivers/polepos.c.html
  4. ^ http://web.archive.org/web/20130104201547/http://mamedev.org/source/src/mame/video/polepos.c.html