Talk:Instruction pipelining

Negation missing?

While reading the page, I saw this sentence:

It therefore allows faster CPU throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate.

Shouldn't that be "wouldn't otherwise be possible"? Seems confusing to me. — Preceding unsigned comment added by V shashenko (talk • contribs) 08:32, 21 June 2016 (UTC)

Hello! The sentence is fine, it compares the pipelined (first part of the sentence) and non-pipelined (the second part) instruction throughputs. Hopefully, this will make it more clear. — Dsimic (talk | contribs) 08:48, 21 June 2016 (UTC)

The need for a negative in constructions like this is a rule of some languages other than English (here I presume Russian). This is also true in Spanish. In English, the hypothetical clause of a comparison is not negated. There is a way to write it not as a comparison: "allows fast CPU throughput...that would not otherwise be possible." But the sentence is fine. Spike-from-NH (talk) 14:56, 22 December 2016 (UTC)

"frequently used in CPUs but avoided in real-time systems"

Aren't most CPUs now pipelined, and aren't most real-time systems based on CPUs? See "11-stage pipeline on the Cortex-R7", for example... 46.218.234.67 (talk) 14:20, 22 December 2016 (UTC)

The comment is well-taken. This sentence ends, "in which latency is a hard constraint." I worked on processors where latency was a hard constraint, and even conditional execution could disturb refresh of the display monitor and make the image jitter. That was last century, and in the real world, the "hard constraint" between the start and end of an instruction is made insignificant by producing a processor that is one hundred times faster. I'll reword this paragraph. Spike-from-NH (talk) 14:39, 22 December 2016 (UTC)

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Proposed merge with Simultaneous multithreading

Simultaneous multithreading is a special case of Instruction pipelining where the fetch phase looks ahead and injects multiple instructions with non overlapping resource utilization into the decode-execute pipeline when possible. Ethanpet113 (talk) 08:20, 3 January 2019 (UTC)

No, it is not simply a special case of instruction pipelining. It isn't just the fetch and decode that are doubled up, many other parts of the pipeline may also have their components doubled up too. Some parts are not doubled, and therefore shared, and some remain single threaded, but not all except the fetch stage.

You can have pipelining with or without SMT and you could have SMT with or without pipelining. You cannot have SMT without the processor being superscalar however.FoxyBuscuits (talk) 10:40, 3 June 2019 (UTC)

Although there are some similarities, those two are quite different techniques. Oppose. --Arny (talk) 13:27, 18 June 2019 (UTC)

Oppose. Should have it's own article. It's a different technology than basic pipelining. Oranjelo100 (talk) 07:10, 19 June 2019 (UTC)

Out of Order Processor Idle Logic

The line "In contrast, out of order computers usually have large amounts of idle logic at any given instant" is on paper often true. However, it is vague and not useful, as the reader will probably assume that this is synonymous with idle execution logic, which is not entirely true. The whole point of OOO processors is that they will keep the ALUS/Multipliers/Dividers/FPUs fed with data by reordering the instructions. The fact that most OOO processors are also superscalar(and so have a tendency to have idle logic when memory bandwidth lmited) is irrelevant to the instruction reordering itself. 2601:246:5900:E790:0:0:0:F1D (talk) 01:41, 22 June 2023 (UTC)