Talk:10 nm process: Difference between revisions
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Talking about the comparison tables. |
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:: I removed a similar section from the [[14 nanometer]] article. Looks like someone literally copy and pasted the same crap there as well. --[[User:CyberXRef|<span style="color:#930014;">Cy</span><span style="color:#4a3f3f;">be</span><span style="color:#007d69;">r</span><span style="color:#05716e;">XR</span><span style="color:#0f5877;">ef</span>]]<sup>[[User talk:CyberXRef|☎]]</sup> 06:12, 12 May 2017 (UTC) |
:: I removed a similar section from the [[14 nanometer]] article. Looks like someone literally copy and pasted the same crap there as well. --[[User:CyberXRef|<span style="color:#930014;">Cy</span><span style="color:#4a3f3f;">be</span><span style="color:#007d69;">r</span><span style="color:#05716e;">XR</span><span style="color:#0f5877;">ef</span>]]<sup>[[User talk:CyberXRef|☎]]</sup> 06:12, 12 May 2017 (UTC) |
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The itrs exists, actually read the corresponding document to see logic device ground rules, will take out unsourced values, rule of thumb thing probably won't mention as it is arbitrary. Again, look at the document and compare to see that they do not meet the logic device ground rules. Some nodes do, and some don't meet these rules, not looking for perfect accuracy but rather to just use it as a third party comparison as a way to move forward measuring process transistor density. Samsung's 10 nm process is better than Intel's 14 nm process discussing strictly density, which is what these articles are for, not electrical properties like performance at different drive currents, which are not discussed here and are a whole different topic entirely then. |
Revision as of 02:59, 13 May 2017
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4 nm demonstration transistor
An Australian team announced that they fabricated a single functional transistor out of 7 atoms that measure 4nm in length. see [[1]] [[2]] Scalzi+ | (Talk | contribs) 21:51, 24 May 2010 (UTC)
- I think we will get to see all the way down to 1nm and perhaps smaller at around 2030. The reason is because of new technology allowing smaller conductor to work in a new environment. 88.88.19.25 (talk) 16:34, 1 February 2011 (UTC)
- The same team has since improved the process to make a transistor out of a single phosphorous atom. Single-atom transistor is 'perfect' Scalzi+ | (Talk | contribs) 22:45, 19 February 2012 (UTC)
Dead link
During several automated bot runs the following external link was found to be unavailable. Please check if the link is in fact down and fix or remove it in that case!
- http://www.semi.org/cms/groups/public/documents/web_content/ctr_030805.pdf --JeffGBot (talk) 02:59, 1 June 2011 (UTC)
- "SEMICON West - Lithography Challenges and Solutions" re 22 nm - still NF - Rod57 (talk) 10:36, 2 January 2016 (UTC)
Dead link 2
During several automated bot runs the following external link was found to be unavailable. Please check if the link is in fact down and fix or remove it in that case!
- "Intel scientists find wall for Moore's Law" - still NF - now seems to be at Intel scientists find wall for Moore's Law - Will use that.
Done Rod57 (talk) 10:41, 2 January 2016 (UTC)
Samsung 10nm
This item does not belong here. It refers to "10 nanometer (nm)-class process technology" This is industry-speak for 1X, ie anything between 10nm and 19nm. It is likely far closer to the latter than the former, so does not belong in an article about the 10nm process. I would just delete it, but I suspect someone will just add it back again, so wanted to note it here first.
156.39.10.21 (talk) —Preceding undated comment added 17:11, 30 April 2013 (UTC)
- Similar items in Technology demos and Mass production. Deleted both as misleading. - Rod57 (talk) 10:54, 2 January 2016 (UTC)
Not an article as it stands
The 10 nanometer (10 nm) node is the technology node following the 14 nm node. << That's the first sentence. This page needs to add some context. — Preceding unsigned comment added by 91.123.162.38 (talk) 22:22, 17 May 2013 (UTC)
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comparison section is garbage
Do not re-add that comparison table and that entire section without discussing it here first because the section I deleted was just nonsense. It was clearly written by people who had no clue what they are talking about.
Problems with that section:
- The ITRS no longer exists
- The ITRS NEVER sets "Ground Rules" EVER. They made a roadmap for the industry BASED ON HOW THE INDUSTRY BEHAVED and create roadmaps based on educated guesses. That means they were often wrong and they self-adjust according as new nodes ramped up. In fact, adjustments were always made after 2 leading nodes ramped up
- Some values in the table were guessed and un-sourecd
- THere is NO SUCH THING AS A 1/3 "rule of thumb" like who the hell seriously wrote that - the reference to that crap is "http://www.eenewseurope.com/news/samsung%E2%80%99s-14-nm-lpe-finfet-transistors/page/0/3" which was the AUTHOR'S OWN ATTEMPT to normalize the node names. It's just his own thing (and btw, it's not even correct).
- "Intel does not satisfy this rule of thumb at around 11 nm," 1) that's someones own personal research and 2) same crap as I pointed out above, no such damn rule 3) it's exactly why the author's own nonsense were incorrect
- "and Intel, Samsung, and TSMC's 10 nm process nodes do not meet all of the International Technology Roadmap for Semiconductors (ITRS) logic device ground rules for this process node." Other than being personal research, note that it's clear whomever wrote it has no clue what they are talking about. If we checked whether the industry node "meets all the ITRS reqs" then NO NODES WOULD. That's because the ITRS ADJUSTS itself after new process nodes come out. Historically speaking the ITRS roadmaps were considerably off (sometimes by an order of magnitude actually). Unfortunately the ITRS no longer exists and therefor the roadmap hasn't been updated.
- "However, as Samsung's 10 nm process is better than Intel's 14 nm process," seriously, who wrote that garbage? First of all, that's not even Wikipedia:NPOV, secondly looking at the IEDM papers the opposite appears to be true (at least as far as drive current is concerned), but thirdly and most importantly, YOU CANNOT MAKE THOSE ASSESSMENTS WITHOUT ACTUALLY EVALUATING THE Process design kit (PDK)!!! A bunch of transistor attributes is insufficient.
Discuss here before adding anything from that section back. --CyberXRef☎ 06:09, 12 May 2017 (UTC)
- I removed a similar section from the 14 nanometer article. Looks like someone literally copy and pasted the same crap there as well. --CyberXRef☎ 06:12, 12 May 2017 (UTC)
The itrs exists, actually read the corresponding document to see logic device ground rules, will take out unsourced values, rule of thumb thing probably won't mention as it is arbitrary. Again, look at the document and compare to see that they do not meet the logic device ground rules. Some nodes do, and some don't meet these rules, not looking for perfect accuracy but rather to just use it as a third party comparison as a way to move forward measuring process transistor density. Samsung's 10 nm process is better than Intel's 14 nm process discussing strictly density, which is what these articles are for, not electrical properties like performance at different drive currents, which are not discussed here and are a whole different topic entirely then.