10 nanometer

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For the length in general and comparison, see 10 nanometres.

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.

As of 2016, 10 nm devices were still under commercial development. Samsung first released their version of a "10 nm" process node in 2017.[1][2]



The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm. Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, claimed in 2008 that Intel saw a 'clear way' towards the 10 nm node.[3][4] At the 11 nm node, Intel expected (in 2006) to be using a half-pitch of around 21 nm, in 2015,[5] Nvidia's chief scientist, William Dally, claimed (in 2009) that they would also reach 11 nm semiconductors in 2015, a transition he claimed would be facilitated principally through new electronic design automation tools.[6]

As of 2014, "10 nm" node was projected to use a metal pitch of 40–50 nm.[7]

This 10 nm design rule is considered likely to be realized by multiple patterning,[8][9][10] given the difficulty of implementing EUV lithography.

Potential technologies[edit]

While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Scientists have estimated that transistors at these dimensions are significantly affected by quantum tunnelling.[11] As a result, non-silicon extensions of CMOS, using III-V materials or carbon nanotube/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics.

The extensive use of ultra-low-k dielectrics (such as spin-on polymers or other porous materials) means that conventional photolithography, etch, or even chemical-mechanical polishing processes are unlikely to be used, because these materials contain a high density of voids and gaps. At the ~10 nm scale, quantum tunneling (especially through gaps) becomes a significant phenomenon.[12] Controlling gaps on these scales by means of electromigration can produce interesting electrical properties.[13]

Quantum tunneling may be advantageous if its effect on device behavior can be understood, and exploited, in the design. Future transistors may have insulating channels. An electron wave function decays exponentially in a "classically forbidden" region at a rate that can be controlled by the gate voltage. Interference effects are also possible;[14] Alternate option is in heavier mass semiconducting channels.[15] Photoemission electron microscopy (PEEM) data has been used to show that low energy electrons ~1.35 eV could travel as far as ~15 nm in SiO2, despite an average measured attenuation length of 1.18 nm.[16]

Technology demos and pre-production.[edit]

In 2012, IBM produced a sub-10 nm carbon nanotube transistor that outperformed silicon on speed and power.[17] "The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies," according to the abstract of the paper in Nano Letters.[18]

In April 2015, TSMC announced that 10 nm production would begin at the end of 2016.[19]

On 23 May 2015, Samsung Electronics showed off a 300 mm wafer of 10 nm FinFET chips.[20]

In c. August 2016, Intel began trial production at 10 nm.[21]

On 17 October 2016, Samsung Electronics announced mass production at 10 nm.[22]

On 29 March 2017, Samsung started preorders for their Samsung Galaxy S8 which uses Samsung's version of a "10 nm" processor.[23]

Shipping devices[edit]

As of mid-2016, semiconductor business Intel, and foundries at TSMC, and Samsung were all expected to ship or begin volume production of 10 nm devices in the first quarter of 2017, with foundry customers for 2017 including Qualcomm (Snapdragon 835) at Samsung, and Apple Inc. and MediaTek at TSMC.[24]

On 21 April 2017, Samsung started shipping their Galaxy S8 which uses Samsung's version of a "10 nm" processor.[25]

10 nm process nodes[edit]

ITRS Logic Device

Ground Rules


(proposed, not yet released)

Process name 11/10nm 10nm
Transistor Fin Pitch (nm) 36 34
Transistor Fin Width 6 8?
Transistor Fin Height 42 53
Transistor Gate Pitch (nm) 48 54
Interconnect Pitch (nm) 36 36


A rule of thumb is that the process node is generally about 1/3 of the transistor fin pitch. Intel's proposed 10 nm process does not satisfy this rule of thumb at around 11 nm and does not meet all of the International Technology Roadmap for Semiconductors logic device ground rules for this process node. Samsung's 10 nm technology is expected to be better than Intel's 14 nm technology but worse than Intel's proposed 10 nm technology. Therefore, Samsung's 10 nm technology is not expected to satisfy the 10 nm rule of thumb or meet all of the 10 nm ITRS logic device ground rules. However, as Intel has not shipped any 10 nm devices yet, this currently gives Samsung a technological lead, respectively.[28][29][30]


  1. ^ Kellex (2016-10-17). "Samsung Starts Production on 10nm Processors, Possibly for the Snapdragon 830". Droid Life. Retrieved 2016-11-23. 
  2. ^ "Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology". news.samsung.com. Retrieved 2016-11-23. 
  3. ^ Damon Poeter. "Intel's Gelsinger Sees Clear Path To 10nm Chips". Archived from the original on 2009-06-22. Retrieved 2009-06-20. 
  4. ^ "MIT: Optical lithography good to 12 nanometers". Archived from the original on 2009-06-22. Retrieved 2009-06-20. 
  5. ^ Borodovsky, Y. (2006). "Marching to the beat of Moore's Law". Proc. SPIE. 6153. doi:10.1117/12.655176. 
  6. ^ "Nvidia Chief Scientist: 11nm Graphics Chips with 5000 Stream Processors Due in 2015". XBit Labs. July 30, 2009. Archived from the original on 2009-09-03. Retrieved 2009-08-27. 
  7. ^ Who will lead at 10nm?
  8. ^ SEMICON West - Lithography Challenges and Solutions
  9. ^ J. Word et al., Proc. SPIE 6925 (2008).[full citation needed][not in citation given]
  10. ^ Intel extending ArF lithography Archived July 14, 2011, at the Wayback Machine.
  11. ^ "Intel scientists find wall for Moore's Law". ZDNet. December 1, 2003. 
  12. ^ Naitoh, Y.; et al. (2007). "New Nonvolatile Memory Effect Showing Reproducible Large Resistance Ratio Employing Nano-gap Gold Junction". MRS Symposium Proceedings. 997: 0997–I04–08. doi:10.1557/PROC-0997-I04-08. 
  13. ^ Kayashima, S.; et al. (2007). "Control of Tunnel Resistance of Nanogaps by Field-Emission-Induced Electromigration". Jap. J. Appl. Phys. 46 (36–40): L907–909. doi:10.1143/JJAP.46.L907. 
  14. ^ Ahmed, Khaled; Schuegraf, Klaus (November 2011). "Transistor Wars: Rival architectures face off in a bid to keep Moore's Law alive". IEEE Spectrum: 50. 
  15. ^ Mehrotra, S.; et al. (2013). "Engineering Nanowire n-MOSFETs at Lg < 8 nm". Preprint. arXiv:1303.5458Freely accessible. 
  16. ^ Ballarotto, V. W.; et al. (2002). "Photoelectron emission microscopy of ultrathin oxide covered devices". JVST B. 20 (6): 2514–2518. doi:10.1116/1.1525007. 
  17. ^ "IBM: Tiny carbon nanotube transistor outshines silicon". Cnet.com. January 30, 2012. 
  18. ^ Franklin, Aaron D.; et al. (2012). "Sub-10 nm Carbon Nanotube Transistor". Nano Letters. 12 (2): 758–762. doi:10.1021/nl203701g. 
  19. ^ "TSMC Launching 10 nm FinFET Process In 2016, 7nm In 2017". 19 April 2015. Retrieved 25 May 2015. 
  20. ^ "Samsung vows to start 10nm chip production in 2016". 23 May 2015. Retrieved 16 July 2015. 
  21. ^ Pirzada, Usman (Aug 2016), "Intel Starts Up 10nm Factory – Trial Production Will Begin This Quarter, 10nm Canonnonlake Processors On Track For 2H 2017", wccftech.com 
  22. ^ [1]
  23. ^ http://www.samsung.com/uk/smartphones/galaxy-s8/performance/
  24. ^ Manners, David, "10nm Lines Up For Q1.", www.electronicsweekly.com 
  25. ^ http://www.samsung.com/us/explore/galaxy-s8/buy/
  26. ^ "Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals". 
  27. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). 
  28. ^ "Samsung's 14 nm LPE FinFET transistors". 
  29. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). 
  30. ^ "Intel's 22nm Tri-Gate Transistors". 

Preceded by
14 nm
CMOS manufacturing processes Succeeded by
7 nm