Computational lithography

Computational lithography (also known as computational scaling) refers to a collection of math-based approaches that came to the forefront of photolithography in 2008 as the semiconductor industry grappled with the challenges associated with the transition to 22 nanometer CMOS process technology and beyond.

Context: industry forced to extend deep UV photolithography

Historically, the progression of stepper illumination sources to smaller and smaller wavelengths — from "g-line" (436 nm) and "i-line" (365 nm) sources based on mercury lamps, to the current systems based on deep ultraviolet excimer lasers sources at 193 nm — has been a driving force behind Moore's Law. The use of smaller wavelength light allows the resolution and printing of smaller geometries on an integrated circuit. However the progression to yet finer wavelength sources has been stalled by the intractable problems associated with extreme ultraviolet lithography and x-ray lithography, forcing semiconductor manufacturers to extend the current 193 nm optical lithography systems until some form of next-generation lithography proves viable (although 157 nm steppers have also been marketed, they have proven cost-prohibitive at $50M each).

Tremendous progress has already been made by using techniques such as immersion lithography and phase-shift photomasks, allowing 193 nm deep UV steppers to go far beyond the Rayleigh criterion to handle 32 nanometer CMOS process technology with some difficulty. However, with the ITRS roadmap calling for the 22 nanometer node to be in use by 2011, photolithography researchers have had to develop an additional suite of improvements to make 22 nm technology manufacturable. While the increase in mathematical modeling has been underway for some time, the degree and expense of those calculations has justified the use of a new term to cover the changing landscape: computational lithography.

Techiques comprising computational lithography

Computational lithgraphy makes use of a number of numerical simulations to improve the performance (resolution and contrast) of cutting-edge photomasks. While many of these techniques have been used individually, their combined use into a systematic mask-making flow delineates computational lithgraphy from earlier efforts. The combined techniques include:

Reticle Enhancement Technology (RET)

Reticle enhancement technology, first used in the 90 nanometer generation, using the mathematics of diffraction optics to specify multi-layer phase-shift photomasks that use interference patterns in the photomask that enhance resolution on the printed wafer surface.

Optical Proximity Correction (OPC)

Optical proximity correction uses computational methods to counteract the effects of diffraction-related blurring and under-exposure by modifying on-mask geometries with means such as:

• adjusting linewidths depending on the density of surrounding geometries (a trace surrounded by a large open area will be over-exposed compared with the same trace surrounded by a dense pattern)
• adding "dog-bone" endcaps to the end of lines to prevent line shortening
• correcting for electron beam proximity effects

Controllable source illumination

Additionally Cadence Design Systems promotes their computational lithography system as being able to adjust stepper illumination levels based on a two-dimensional analysis of the geometries being exposed.

Complex modeling of the lens system and photoresist

Beyond the models used for RET and OPC, computational lithographics attempts to improve chip manufacturability and yield by modeling a number of other factors:

• polarization characteristics on of the lens pupil
• Jones matrix of the stepper lens
• optical parameters of the photoresist stack
• diffusion through the photoresist
• stepper illumination control variables

A CPU-century worth of calculations or more

The computational effort behind these methods is immense. According to one estimate, the calculations required to adjust OPC geometries to take into account variations to focus and exposure for a state-of-the-art integrated circuit will take approximately 100 CPU-years of computer time. This does not include modeling the 3D polarization of the light source or any of the several other systems that will to be modeled in production computational photolithographic mask making flows. Brion Technologies, a subsidiary of ASML, the largest manufacturer of photolithography systems, markets a rack-mounted hardware accelerator dedicated for use in making computational lithographic calculations — a mask-making shop can purchase a large number of their systems to run in parallel.