Talk:Front-side bus

MT/s vs MHz: The debate rages on, but why?

I just posted a discussion over on the Intel Core 2 discussion page about this -- why are we listing front side buses in megatransfers per second (MT/s)? This article states (incorrectly, I might add) that, quote; "Many manufacturers today publish the speed of the FSB in megatransfers per second (MT/s), not the FSB clock frequency in megahertz (MHz)." No manufacturer lists their front side bus in MT/s! They may list the speed of their newfangled, high speed, point-to-point interconnects as MT/s... but no one measures their FSB in MT/s! Look at any retail website selling these chips, or even retail websites selling complete systems. Why not take it straight from the horse's mouth, from Intel's on-site documents [1]? A Pickle (talk) 04:35, 29 June 2009 (UTC)

Becaus ethey use fake MHz, they do not use the MHz the Bus runs at but instead the data rate (bus clock x data blocks transferred per clock). In effect they use MT/s but state is as MHz because it sounds and sells better to those who do not know much about computers. --Denniss (talk) 17:53, 29 June 2009 (UTC)

FSB/Core ratio clock multiplier

What I need to know is :which is better, makes for a faster computer that does not sieze up, a high or low fsb/core ratio-clock multiplier? I get confused between the explanations using one concept or the other.

George Staffa (talk) 02:00, 11 December 2008 (UTC)

Neither - the two parameters are basically opposed to each other. If you have a machine with a low core:bus ratio (e.g. 1:1) you won't stall the processor but technical limitations mean that you can't ramp up the clock speed. Such a chip might never stall but won't run faster than a couple of hundred MHz. If you have a chip that runs it's FSB at that same speed but its core at something faster you aren't going to lose anything. Even in the worst possible case the chip will still have the same speed as the 1:1 processor, but on average it will be substantially faster, even if it does stall occasionally.

Current microprocessor developments are basically taking the high core:bus ratio approach for this reason, but are focussing on introducing ways to mitigate the effects of stalling. There are two main approaches. The first is the obvious - use faster/smarter caches to reduce the amount of cache misses that occur. The other approach is to design your cores so that they can quickly switch to another task if a stall occurs so that they can continue to do something constructive while they await fresh data from memory. This is what Intel's Hyperthreading was all about and is an approach taken to its logical conclusion with Sun's Niagara CPUs. There is not fundamental reason why both approaches can't be combined but limited chip areas and R&D budgets tend to lead to a primary focus on one idea or the other. —Preceding unsigned comment added by CrispMuncher (talk • contribs) 11:15, 11 December 2008 (UTC)

Yes

having L2 cache on the processor die itself, this

It will be better if it changes to like this :

having L2 cache on the die of the processor itself, this —Preceding unsigned comment added by 60.50.228.27 (talk) 02:12, 23 June 2008 (UTC)

Gramatical error?

having L2 cache on the processor die itself, this

processor die? I'm no expert on buses, but either this was not intentional or this para graph needs changing.

No, it's not an error- there is, as far as I know, actually a thing called the processor die.--Airplaneman (talk) 19:58, 29 May 2009 (UTC)

No

No, this is not an error. Die is waver texture in circuits.

Asynchronous FSB/SDRAM bus speeds

"Similar to the PCI and AGP buses, however, the memory bus can sometimes also be run asynchronously from the front side bus." A good point is made here, but the text only mentions bus ratio settings. Some chipsets allow different memory bus speed settings; such as SDRAM=FSB or SDRAM=FSB+33. It would be nice to see that in the text also...

FSB chart

There seem to be quite a few FSB800 Pentiums flying around these days: the article is either outdated or needs an explanation. --Tom Edwards 20:33, 17 July 2005 (UTC)

Can u explain me how to do overclocking in a P4 2.0 system with 845 mother board...

please tell me how to overclock the system..

Try a forum

---

Athlon XP

Weird, my PC with an Athlon XP processor only supports FSB 100/133/166 o.Ô

I have an Athlon XP 2600, which only goes upto 166mhz front side bus. This is thus 333MHz when doubled. I just recently put new RAM in the machine that is DDR-400 (400MHz memory speed when doubled, as per usual DDR semantics). My BIOS supports asynchronous bus speeds for FSB and RAM. This article seems to suggest that I should underclock my RAM to 333MHz to match the FSB of the CPU, without being explicit. What's the proper thing to do in my case, and can the article be expanded on to eliminate this ambiguity? 86.139.204.252 21:03, 3 May 2006 (UTC)

Your XP runs with 166 MHz FSB and your memory with max 200 MHz. IF you have an nForce2 system then use both with 166 MHz unless you want to OC your CPU, using different speed on FSB and memory slows own your system. Most other Sockt-A system should run fine with memory clocked higher than FSB. --Denniss 22:59, 3 May 2006 (UTC)

abbreviation

wiki seaching fsb didnt point to this article

there are other uses to FSB. --202.71.240.18 07:11, 13 July 2006 (UTC)

speed examples a bit dated

in the CPU section: "For example, a processor running at 550 MHz might be using a 100 MHz FSB." These speeds kind of date the article a bit don't you think. Should moore's law be applied here?

Transfers 4 times per clock?

From the first note in the "Some sample FSB frequencies and bandwidths" table: "... and Intel Core 2 processors use a front side bus that transfers data four times per cycle".

Isn't this misleading? From my understanding, the Intel bus usn't really "quad pumped" (whatever that really means) or transferring data four times per clock cycle. Yes, it is transferring 4 times as much data as a system transferring one set of data per clock, but it does this by using pairs of memory DIMMs (128-bit memory bus width, compared to the standard 64-bit), and double data rate (transferring data on both the rising and falling clock edges). That way, the signals don't have to change state faster than the clock already does, so you get maximum data transfer with existing bus technology. The cost is that you need more wires on the mother board, and you need to use pairs of memory modules (or suffer massive performance penalties).

There seems to be a lot of confusion over this. I've seen web pages with sinusiodal clocks, transferring data at the peaks and also the zero crossings of the sine wave! Please! So I'd echo the calls for decent diagrams on how this works. --Mike Van Emmerik 00:49, 6 October 2006 (UTC)

Intel "quadpumped" (I really don't like this word) FSB transfer 4 packets of data regardless of what memory is installed (even with SDR-SDRAM).

Interesting, and I agree with "4 packets of data" or similar, but what's said is "4 times per cycle" implying that on a processor with a "1066MHz FSB" there are four transfers (presumably, evenly spaced) per 267MHz clock cycle, which by my understanding is not true. (I believe that there are two transfers, evenly spaced, in each 267MHz cycle, each of these from two separate DIMMs.) In other words, there is a doubling in time, and a doubling in data width, not a quadrupling in time, as is implied by the article as currently written. --Mike Van Emmerik 10:02, 8 October 2006 (UTC)

4 pieces of data are trasnferred even with a single memory stick installed as this even works with single-channel memory. I'm not really the expert on how and when data is transferred but I think to remeber it will be transferred at the raising and the falling clock signal as well as on the peak ond the bottom. Try a gogle search to find out more. --Denniss 09:47, 9 October 2006 (UTC)

This is how it's done: Each bus clock cycle the 64-bit databus can transfer 4 packets. The bus clock is 266mhz on modern intel parts. This provides for an effective data rate of 1066mhz, 64bit transfers, resulting in peak throughput of 8B * 1.066GHz = 8.5GByte/s. This has nothing to do with the memory speed, that is a totally different bus.

Isn't that called "Quad Data Rate" (QDR)? --202.40.137.202 03:51, 12 April 2007 (UTC)

Don't you confuse the FSB with DDR? The DDR(2) memory can do only two transfers per clock indeed. But FSB can do 4. Their coupling (either by entailing two memory banks/channels for full utilization or reducing FSB speed) is another story. --Javalenok (talk) 08:26, 6 July 2009 (UTC)

80.191.148.141 02:33, 13 October 2006 (UTC)

I've seen many pages on Internet that say Hypertransport 2GHz or 2000MT/s.

Do they refer to Hypertransport 1GHz Version. If your answer is (yes),

explain it and write about Intel's 1066 MT/s FSB.

In fact , write what we need to compare two FSB. (Hyperthreading , Intel's FSB)

( 1000MHz,1066Mhz or 8000MB/s,8533MB/s or 2000MT/s,1066MT/s )

All beginners like me are always confused and give their money to these companies.

I think this Article want a section about bus width. ( I mean 32 bit or 64 bit ,... )

Also, explain more about the 14400MB/s Bandwidth You've written for Hypertransport.

Finally, Please explain about FSB bandwidth increase. Will an Amd 3000+ (1800 MHz)

work better with Hypertransport 1GHz rather than Hypertransport 800MHz.

Beacuse both of them have 200 MHz system clock.

FSB Memory Bus Ratio

The article asserts:

For example, the current Core 2 architecture seems to perform better at a 1:1 ratio (that is, FSB1066 - true 266 MHz * quad-pumping - and DDR2-533 - true 266 MHz * double pumping) than a 4:5 ratio (using DDR2-667), but stepping it up to a 2:3 ratio (DDR2-800) or higher seems to increase performance over a 1:1 ratio.

Although no justification or reference is provided.

All-in-all the FSB topic is very important and this article really needs to be rewritten by someone with a deep technical understanding and practical experience in overclocking.

Removed

I removed this from the article because I don't think it directly adds to the article, but we might want to put it somewhere else so I put a copy here.

Three recent bus technologies are GTL+, EV6, and HyperTransport. Each bus is unique in how it moves data within the system between the CPU and devices.

GTL+/AGTL+ Bus

• Designed by Intel for the Pentium Pro, Pentium II, and Pentium III CPUs, as well as Xeons based on these cores (GTL+)
• Redesigned for the Pentium 4 as well as Xeons on the same cores (AGTL+)
• So-called because it uses GTL+ signalling
• VIA's C3, C7, and Epia CPUs use these buses and are often interchangeable with Intel CPUs
• A "shared" bus, meaning that all CPUs compete over the same physical connection for the bus' bandwidth.

EV6 Bus

• Designed by DEC (now part of HP) for use with their Alpha EV6 CPUs
• Licensed by AMD for their Athlon and Athlon XP line of CPUs
• A point-to-point protocol connecting each CPU to the northbridge, meaning that each CPU has a dedicated connection to the device.

HyperTransport

• Designed largely by AMD in conjunction with the HyperTransport Consortium
• A point-to-point serial connection used by AMD for their Athlon 64, Athlon FX, Athlon X2, and Opteron processors.
• Not technically a front side bus.
• The HyperTransport connection connects AMD CPUs to the rest of the system. Also, these CPUs use it as the baseline to which the internal clock multiplier is applied. Both of these functions were traditionally performed by the frontside bus. On AMD-64 CPUs, the frontside bus, which connects the CPU to the northbridge, has been removed in favor of an on-die memory controller which communicates with RAM directly.

removed

This is a really nicely formatted table, but does it really add to the article on FSB? Is it too Intel-centric? I removed it but copied it here because it has such nice format.

re:removed

Why is it too intel-centric, when AMD products had been added into discussion? —Preceding unsigned comment added by 60.50.228.27 (talk) 02:14, 23 June 2008 (UTC)

Some sample FSB frequencies and bandwidths

Processor Class	FSB Frequency	FSB Type	Theoretical Bandwidth
Pentium II	66/100 MHz	GTL+	533/800 MB/s
Pentium III	100/133 MHz	GTL+	800/1066 MB/s
Pentium 4*	100/133/200 MHz	AGTL+	3200/4266/6400 MB/s
Pentium M*	100/133 MHz	AGTL+	3200/4266 MB/s
Pentium D*	133/200 MHz	AGTL+	4266/6400 MB/s
Pentium 4 EE*	200/266 MHz	AGTL+	6400/8533 MB/s
Intel Core*	133/166 MHz	AGTL+	4266/5333 MB/s
Intel Core 2*	166/200/266 MHz	AGTL+	5333/6400/8533 MB/s
Xeon - P6 core	100/133 MHz	GTL+	800/1066 MB/s
Xeon* - Netburst core	100/133/166/200/266 MHz	AGTL+	3200/4266/5333/6400/8533 MB/s
Xeon* - Woodcrest core	266/333 MHz	AGTL+(with Dual Independent Buses)	17066/21333 MB/s
Athlon/Duron**	100/133 MHz	EV6	1600/2133 MB/s
Athlon XP/Sempron**	133/166/200 MHz	EV6	2133/2666/3200 MB/s
Athlon 64/X2/Opteron***	600/800/1000 MHz	Hypertransport	7500/12800/14400 MB/s
PowerPC 970****	450/500/625 MHz	Elastic	7200/8000/10000 MB/s
Notes: * - Pentium 4, Pentium M, Pentium D, Pentium EE, Xeon, Intel Core, and Intel Core 2 processors use a front side bus that transfers data four times per cycle ** - Athlon and Athlon XP processors use a front side bus that transfers data twice per cycle (Double data rate) *** - Athlon 64, FX, and Opteron processors have a memory controller on the CPU die, which replaces the traditional FSB. The bus specifications given here are for the HyperTransport link and memory bandwidth. **** - PowerPC 970 processors use a front side bus that transfers data twice per cycle (Double data rate)

If the PowerPC 970 has a FSB DDR, how does it get higher transfer speeds at a lower clock than other DDR FSBs? Or maybe I'm confused about that. - MSTCrow 16:36, 29 October 2006 (UTC)

I think the speed entries for it are wrong. According to PowerPC 970, the FSB runs at half the clock speed, and clock speed varies from 1.6GHz to 2GHz, so the FSB should be 800-1000MHz, not 450-625MHz as is in the table. One of these is wrong, and as you point out a discrepancy in the table data, I'm inclined to believe it's the table. JulesH 09:43, 9 December 2006 (UTC)

Info Box?

Does the infobox at top right look right to people? (I can't decide so I'm not touching it for now.) RJFJR 11:59, 28 October 2006 (UTC)

I've removed the infobox, because it just doesn't seem appropriate to this article. It's designed for describing particular bus designs, not the logical purpose that a bus may serve, which is what this article is about.

As an example of the problem this causes, the box said width was "32 or 64 bits", whereas an FSB can really be any size. The FSB on a 286, for example, is 16 bits. The FSB on a Core 2 Duo is 128 bits, I believe (i.e., it has 2 independent memory access channels of 64 bits each). As somebody has mentioned below, some processors have serial interfaces as part of their FSB as well. —The preceding unsigned comment was added by JulesH (talk • contribs) 09:33, 9 December 2006 (UTC).

Serial FSB

How do I include serial into the infobox, as Hypertransport can be serial in nature? Also, I think the FSB can be a minimum of 2 or 4 bits in width. Thanks. - MSTCrow 16:34, 29 October 2006 (UTC)

"Most motherboards allow overclocking?"

Near the end of the article, under "Overclocking," there is a sentence that reads: "Most motherboards allow the user to manually set the clock multiplier and FSB settings by changing jumpers or BIOS settings."

Where is the source for this? The last time I checked, most PCs were bought pre-assembled and preloaded with software, from companies such as Dell, HP, eMachines, etc. The majority of these PCs and motherboards within DO NOT allow you to change the FSB, much less multiplier. Perhaps a change is needed? The only motherboards that enable one to change the FSB and multiplier settings are chips purchased for custom-built computers, which represent a minority in the PC world. Thoughts? Opinions? -- Punchinelli 19:37, 2 November 2006 (UTC)

Update: I added and edited some info in the aforementioned Overclocking section to yield a more accurate representation of the amount of overclockable motherboards. Punchinelli 21:49, 14 November 2006 (UTC)

Webopedia?

That article is not much more than a sentence, I do not believe that it would really help unless someone disagrees with me. VentusIgnis 13:18, 4 March 2007 (UTC)

"Frontside" versus "Front side"

Frontside - please check any dictionary to see that there is no such word in English. It is "Front side bus". --Kubanczyk 09:10, 24 September 2007 (UTC)

Shonky math, or missing precision?

The MT/s is affected by how many ticks are performed for each mhz, so if a motherboard has a 266MHz FSB and performs 4 transfers per clock tick, it has a total data transfer rate of 1066 MT/s. That is what the manufactures give as the speed of the FSB. Intel calls this technique which has 4 ticks per cycle Quad Pumping.

266 * 4 = 1064, not 1066. Should that be 266.5MHz, or is the 1066 MT/s wrong? —Preceding unsigned comment added by 59.167.247.10 (talk) 05:48, 10 December 2007 (UTC)

Missing pieces

It seems like this article is missing something. In the "pros and cons" section, it talks about the FSB like there are alternatives to it, but in the article above that, it talks as if there isn't any other way for the memory/system components/northbridge to communicate with the processor. This definitely needs to be fixed, because this reads sort of like a half-article right now. Like a lot of stuff was cut out of the article that made it make sense at some point in the past. (Some of which seems to be here on the talk page.) RobertM525 (talk) 01:40, 15 December 2007 (UTC)

That entire section needs rewriting and sourcing as it currently reads like a personal analysis. The section should be titled something like "Criticism" or "Obsolescence". With regard to AMD specifically, the alternative being implied is HyperTransport. Ham Pastrami (talk) 17:17, 15 December 2007 (UTC)

System Bus

I haven't found much in the way of a formal definition of "system bus". I *think* that "system bus" is the same as "fsb", but I'm not sure. Can anyone address this?--75.152.173.147 (talk) 18:50, 23 September 2008 (UTC)

They are pretty much the same. Technically, "FSB" should be a subsection in an article titled "system bus", as "system bus" is the generic term and "FSB" is Intel terminology. Rilak (talk) 08:34, 24 September 2008 (UTC)

I've seen the term "PSB" (processor side bus) sporadically around the internet, with inconsistent definitions. What is the difference, if any, between "PSB" and "FSB"?132.38.190.10 (talk) 19:30, 29 July 2009 (UTC)