Jump to content

Talk:Haswell (microarchitecture)

Page contents not supported in other languages.
From Wikipedia, the free encyclopedia

This is an old revision of this page, as edited by Vivil (talk | contribs) at 18:44, 11 February 2017 (→Requested move 11 February 2017: Left reply.). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

rPGA947 or FC PGA946?

Intel Socket G3, also known as rPGA 946B/947 or FCPGA 946. — Preceding unsigned comment added by 181.47.181.53 (talk) 21:47, 16 November 2016 (UTC)[reply]

"Thermal problems" section

Hey Jesse Viviano! I've just deleted "Thermal problems" section you've added earlier, and I'll try to explain that further. The content this section provided is somewhat not-so-encyclopedic, as it's based on one source and a few forum posts. I know, it's all most probably true, and I've watched numerous Haswell delidding videos on YouTube myself – but to me, it might be better to leave that on YouTube instead of incorporating it into a Wikipedia aricle. At the same time, improved TIM is already covered in Haswell (microarchitecture) § Haswell Refresh section. Hope you agree, and I'm more than open for further discussion. — Dsimic (talk | contribs) 01:31, 29 August 2014 (UTC)[reply]

Dude, the TIM is ***NOT*** the issue, and NEVER was, and this has been scientifically proven. The problem is the gap between the top of the die and the IHS.[1] This section reads like the marketing literature which says the TIM is the problem without telling people that the IHS does not physically even touch the die. This problem PERSISTS in Devil's Canyon. Average temperature decrease seen as a result of delidding a Devil's Canyon is on the order of 10-20C, in extreme cases, up to 30C. The i7-4790K I am typing this from (4.7 GHz @ 1.295Vcore / 4.3 GHz @ 1.200Vuncore) saw a temperature drop of between 14C and 16C simply by delidding. The delidding removes the gap by getting rid of the true cause of the problem, the epoxy holding the IHS down, which apparently lifts the IHS as it cures. See: [2][3] Is this page an encyclopedia of knowledge, or marketing to cover Intel's ass? Oh, and although I don't have the reference handy at the moment, the OFFICIAL explanation is that since the Ivy Bridge shrink, the mainstream CPUs are too small to handle the heat of soldering the die to the IHS without a large number of them cracking, thus the use of the TIM and excessive epoxy. LGA 2011 and 2011-3 are large enough dies that this is not an issue. The gap issue is of serious enough importance on the K SKUs (or mainstream SKUs in SFF chassis) that it seriously needs mention in this entry. People researching a USD$330 purchase need to have the correct information. The cure to the problem is delidding, remove the TIM and epoxy residue, protect the VRMs with liquid electrical tape or clear nail polish, replace the TIM on the die with a liquid metal TIM, of which there are now multiple manufacturers (Coolaboratory's Liquid Pro and Liquid Ultra, Gelid's Indigo Extreme), and return the IHS to it's position on top of the die, which now sits directly on top of and in contact with the die. As it sits, this article is giving patently false information concocted by Intel's MARKETING department to DECEIVE people into thinking that the earlier issue with Ivy Bridge and Haswell mainstream SKUs has been solved. Is Wikipedia in the deception business (a lot of people will give a simple yes to that on probably 20% of the pages at this site)? Given the leaked picture of the die of the i7-5775C, it is plainly obvious that this problem does extend to the Broadwell as well, and will probably extend to the Skylake as well. The basic problem is die size, so, unless they increase the transistor budget to increase the size of the mainstream dies (unlikely), this will be an issue for the foreseeable future. Currently, Wikipedia is three Intel generations behind on telling people about this problem that has been confirmed by many thousands of people worldwide. 69.49.217.158 (talk) 09:19, 15 May 2015 (UTC)[reply]
Here is a proposed add-in section: "Although the TIM improvement, and especially the use of less epoxy, did make the notorious IHS to Die gap smaller, the gap itself, and it's thermal issues that have existed since the Ivy Bridge shrink on the mainstream SKUs still persists, often to the same extent as in Haswell. An Intel Engineer went public [reference] explaining that the Ivy Bridge and subsequent shrinks made the mainstream dies too small to solder to the IHS without excessive numbers of dies cracking as a result. At normal stock speeds, properly cooled, this is not normally a problem, but in Small Form Factor (SFF) Chassis, and in overclocking, this is a serious issue that has been solved by a procedure known as "delidding", which removes the gap completely, resulting in increased longevity as a result of near-perfect heat transfer to the IHS, although it does void the warranty. [references to above cited encyclopedic sources on the subject]" 69.49.217.158 (talk) 10:06, 15 May 2015 (UTC)[reply]
Is it "encyclopedic" to accept marketing claims over verifiable experience? I don't see any evidence that "improved TIM" was successful in reducing temperatures. The problem persisted. That is the experience of computer enthusiasts. It may be difficult under the Wikipedia citation system though to find an acceptable source for this. We are left with a situation where published but incorrect information is perpetuated. Intel did put forward a number of explanations regarding the cause of high temperatures, including the one cited in the post above. Seasalt (talk) 12:28, 15 May 2015 (UTC)[reply]
As we know, Wikipedia requires reliable sources and forum posts aren't considered as such. Sorry, that's how it works. By the way, how do you know that the 0.06 mm gap between the die and heat spreader isn't there on purpose to compensate for thermal stresses during the CPU operation, for example? — Dsimic (talk | contribs) 13:52, 15 May 2015 (UTC)[reply]
Because the delidding/relidding process removes thermal stresses. This is Thermal management 101. The annealing temperature of single-crystal silicon is so high it would literally fry any circuit on it. Try "A Heat Transfer Textbook" (Lienhard and Lienhard, Third Edition, 2004, Phlogiston Press) for an explanation. Also the sloppiness, and wide variation points simply to a well known principle of how epoxy hardens, this sloppiness and variation is seen in practice. If it were to account for some undocumented (anywhere) thermal issue where MORE heat is needed, it would require uniformity and tight tolerances. Still trying to find that source on the Intel engineer, I have it or had it. Also, there are now several companies doing this as a service. "Silicon Lottery" is such a company, Aeri, others... I've seen that quoting marketing literature and sites is acceptable here, correct? 69.49.217.158 (talk) 18:46, 15 May 2015 (UTC)[reply]
Do thermal industry pubs count? "Wind-Tunnel Cooled Computer May Help Cure Cancer", ("Electronics Cooling", Jan. 4, 2013) [4] 69.49.217.158 (talk) 19:13, 15 May 2015 (UTC)[reply]
Perhaps I didn't write it clearly enough, sorry. How do we know that the 0.06 mm gap between the die and heat spreader isn't there to compensate for thermally induced expansion of materials making up the whole processor? I'm by no means an expert in that area, but many things aren't as straightforward as they seem at the first look. — Dsimic (talk | contribs) 19:23, 15 May 2015 (UTC)[reply]
First, the gap is not consistent, and is proportional to the gobbing of epoxy, thus such a wide bell curve of deltas (mine was actually at the mean) from under 10C all the way to 30C. Second, this has been an issue for MANY years. "Four Decades of Research on Thermal Contact, Gap, and Joint Resistance in Microelectronics", (Yovanovich, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES , VOL. 28, NO. 2, JUNE 2005) [5] 69.49.217.158 (talk) 19:28, 15 May 2015 (UTC)[reply]
Hm, when looked at by a non-expert in the area such as myself, it all pretty much makes sense. Also, Intel probably wants its CPUs to have as less redundant cooling potential as possible, as that reduces their overclokability and forces people to buy more expensive variants if higher operating frequencies are desired. However, we'd need reliable sources and, as I already wrote earlier, forum posts unfortunately aren't considered as such. — Dsimic (talk | contribs) 19:48, 15 May 2015 (UTC)[reply]
Well, I'm still searching my links and the net for authoritative sources acceptable here. One problem is that such companies actively use Bush-style cutoff tactics against people who speak of things they would rather avoid discussion on (I wish Obama would do what Bush did to certain "Journalists", instead of just ridiculing them). The proposed text clearly implies that this is largely a factor only on the K SKUs and in the SFF use-case where thermal issues rear their ugly head the most. For the standard SKUs in larger well-ventilated cases, with aftermarket air or water cooling solutions, this is not an issue. Unfortunately, it is an issue for their most expensive chips most suited to these two use-cases. The upcoming Broadwell i7-5775C may indeed produce references to the problem that would be considered "reliable sources" here, as given the specs, and the delidded chip picture leaked this week, it's obvious that to get anywhere close to i7-4790K performance, they will indeed have to be delidded, meaning more mainstream pubs will be referencing the need to do so. Let's call that an educated guess. 69.49.217.158 (talk) 22:19, 15 May 2015 (UTC)[reply]
  1. ^ "Proof that the benefit from Delidding is entirely due to reducing the CPU-to-IHS gap".
  2. ^ "Official Delidded Club Guide".
  3. ^ "The Intel Devil's Canyon Owner's Club".
  4. ^ ""Wind-Tunnel Cooled Computer May Help Cure Cancer", ("Electronics Cooling", Jan. 4, 2013)".
  5. ^ ""Four Decades of Research on Thermal Contact, Gap, and Joint Resistance in Microelectronics", (Yovanovich, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES , VOL. 28, NO. 2, JUNE 2005) )" (PDF).

Table sorting

Hello, Timeshifter! Regarding my edit that removed sorting from one of the article's tables, the rationale is that no sorting is available for other tables in the article, or in similar tables in Sandy Bridge, Ivy Bridge (microarchitecture), and other similar articles. Thus, having the sorting available in only one table in only one of such articles is simply inconsistent, and‍—‌quite frankly‍—‌looks really ugly with a separate row containing only the sorting arrows. Also, the "instructions" you've added are simply out of place. — Dsimic (talk | contribs) 13:34, 30 March 2015 (UTC)[reply]

You are obviously a newb concerning table sorting. It is on thousands and thousands of tables on Wikipedia. So are various sorting instructions. And you should explain such reverts on the talk page BEFORE deleting something as common as sorting tables. It was hard work to make this table sortable. --Timeshifter (talk) 13:36, 30 March 2015 (UTC)[reply]
With over 27,000 edits I could hardly be considered a newbie. Moving forward, can you put sorting arrows into the table heading? If that's doable, and if you're willing to do it consistently for all tables in the article, I'd say go for it. — Dsimic (talk | contribs) 13:38, 30 March 2015 (UTC)[reply]
The reason to have a separate row of sorting headers in this case is because it is a wide table. See the relevant section of Help:Sorting. Section currently titled: "In a narrow space: sorting buttons in a separate row". I have edited Help:Sorting extensively. If the sorting arrows are put in the text cells, then the text cells are wider, and more of the table extends past the right side of the screen on narrower screens. I just did the math, and I have around 125,000 edits total on Wikipedia, Commons, other Wikimedia Projects, Wikia, and Shoutwiki. --Timeshifter (talk) 13:53, 30 March 2015 (UTC)[reply]
I've read that guideline, but I don't see that as a valid argument, simply because only a few columns would be widened by adding the sorting arrows. — Dsimic (talk | contribs) 13:58, 30 March 2015 (UTC)[reply]
Believe me, it adds up. It really irritates a lot of people to have to scroll horizontally. It can be hard enough to have to follow a column down past the bottom of the screen, and then have to remember the column heading. It is easy to mix up columns. To add horizontal scrolling to the mix makes it doubly confusing. The less the better. --Timeshifter (talk) 14:05, 30 March 2015 (UTC)[reply]
I already have to scroll on a 13-inch screen, and I don't complain. Why are you against using an {{Efn}} note? It goes along with your "the less the better" approach. — Dsimic (talk | contribs) 14:16, 30 March 2015 (UTC)[reply]
Timeshifter, are you willing to discuss this further? — Dsimic (talk | contribs) 18:01, 31 March 2015 (UTC)[reply]
I am taking this off my watchlist. There are many other article editors that appreciate sorting more than you do. So why stress myself over any one particular article. I originally added the sorting to satisfy my own needs while researching wattage, speed, price, etc. of CPUs. --Timeshifter (talk) 21:29, 2 April 2015 (UTC)[reply]
I appreciate everyone's work, but discussing the things and reaching reasonable compromises is the key. — Dsimic (talk | contribs) 05:56, 5 April 2015 (UTC)[reply]

Wrong classification

I believe these cpu : 5820K , 5930K , 5960X are not Haswell , they are Haswell-E . — Preceding unsigned comment added by 87.71.48.161 (talk) 09:18, 8 May 2016 (UTC)[reply]

They are still based on the Haswell microarchitecture. — Dsimic (talk | contribs) 01:56, 3 June 2016 (UTC)[reply]

Requested move 11 February 2017

– The current title is nonsensical and the vast majority of articles like this use "(microarchitecture)" (see here). As stated in the lead, these articles are about processor microarchitectures and are used in hundreds of different CPU models, so "(CPU)" is factually wrong. Pages like Zen (microarchitecture) are using the correct name (in fact all AMD articles use the correct name and so do most Intel). Additionally, the category for this page is Category:Intel microarchitectures. Some of the pages were moved from the correct name without consensus. Laurdecl talk 05:17, 11 February 2017 (UTC)[reply]

This proposed move seems obviously correct to me. Thue (talk) 15:07, 11 February 2017 (UTC)[reply]
The problem is that these are all (with one exceptions) both CPUs and microarchitectures. It is not always so. And actually Kaby Lake is not a microarchitecture, it is a CPU or Intel generation with the SkyLake microarchitecture.Carewolf (talk) 15:41, 11 February 2017 (UTC)[reply]
@Carewolf: I disagree. Kaby Lake is a new microarchitecture (µarch). Smaller number of things are different in this one compared to last few released by Intel but that doesn't mean it's not different µarch. There are number of changes which are quite significant. For example Speed Shift v2. Please use {{Reply to}} Vivil 🗪 18:30, 11 February 2017 (UTC)[reply]
Support. Microarchitecture is accurate description of the topic covered by those pages.
While this is good quick fix I don't see why should we use such name for all of those articles. Let's take Kaby Lake for example. The only topic on Wikipedia with such name is one about the microarchitecture. We should just name it just "Kaby Lake". We didn't name article about Slovenia "Slovenia (country)" because it's currently only use of said name. Please use {{Reply to}} Vivil 🗪 18:43, 11 February 2017 (UTC)[reply]
Retrieved from "https://en.wikipedia.org/w/index.php?title=Talk:Haswell_(microarchitecture)&oldid=764925899"