CDC 6000 series

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The CDC 6000 series was a family of mainframe computers manufactured by Control Data Corporation in the 1960s.[1] It consisted of CDC 6200[2], CDC 6300,[3], CDC 6400, CDC 6500,[4] CDC 6600 and CDC 6700.[5] computers, which were all extremely rapid and efficient for their time. Each was a large, solid-state, general-purpose, digital computer that performed scientific and business data processing as well as multiprogramming, multiprocessing, Remote Job Entry, time-sharing, and data management tasks under the control of the operating system called SCOPE (Supervisory Control Of Program Execution).[6][7] By 1970[8] there also was a time-sharing oriented operating system named KRONOS[9].

CDC 6600 computer. Display console shown in the foreground, main system cabinet in background, with memory/logic/wiring to the left and middle, and power/cooling generation and control to the right.

These large-scale, solid-state, general-purpose digital computing systems[10] were part of the first generation of supercomputers.[11]

The 6600 was the Flagship of Control Data's 6000 series.[12][13]


The CDC 6000 series computers were composed of four main functional devices:

Members of the 6000 series members were reduced instruction set (RISC) machines many years before such a term was invented and had a distributed architecture. They differed primarily in the number and kind of central processor(s):[18]

  • The CDC 6500 was a dual-CPU system: two 6400 processors
  • The CDC 6700 had two CPUs: a 6600 and a 6400[19]

Certain features and nomenclature were also used in the CDC 3000 series:

The only running CDC 6000 series machine, a 6500, has been restored by Living Computers: Museum + Labs[23] It was built in 1967 and used by Purdue University until 1989 when it was decommissioned and then given to the Chippewa Falls Museum of Industry and Technology before being purchased by Paul Allen for LCM+L.[24]


The first member of the CDC 6000 series was the first supercomputer CDC 6600, designed by Seymour Cray and James E. Thornton in Chippewa Falls, Wisconsin. It was introduced in September 1964 and performed up to three million instructions per second, three times faster than the IBM Stretch, the speed champion for the previous couple of years.[25][26] It remained the fastest machine for five years until the CDC 7600 was launched.[27] The machine was Freon refrigerant cooled.

Control Data manufactured about 100 machines of this type,[28] selling for $6 to $10 million each.

The next system to be introduced was the CDC 6400, delivered in April 1966. The 6400 central processor was a slower, less expensive implementation with serial processing, rather than the 6600's parallel functional units. All other aspects of the 6400 were identical to the 6600. Then followed a machine with dual 6400-style central processors, the CDC 6500, designed principally by James E. Thornton, in October 1967. And finally, the CDC 6700, with both a 6600-style CPU and a 6400-style CPU, was released in October 1969.

Subsequent special edition options were custom-developed for the series, including:

  • Attaching a second system configured without a Central Processor (numbered 6416 and identified as "Augmented I/O Buffer and Control)[16]:Appendix A to the first; the combined total effectively was 20 peripheral and control processors with 24 channels, and the purpose was to support additional peripherals and "significantly increase the multiprogramming and batch job processing of the 6000 series." (A 30-PPU 6600 machine was operated by Control Data's Software Research Lab during 1971-1973, but this version was never sold commercially.)
  • Control Data also marketed a CDC 6400 with a smaller number of peripheral processors:[16]:Appendix E
    • CDC 6415-7 with seven peripheral processors
    • CDC 6415-8 with eight peripheral processors
    • CDC 6415-9 with nine peripheral processors


Central memory[edit]

In all the CDC 6000 series computers, the central processor communicates with around seven simultaneously active programs (jobs), which reside in central memory. Instructions from these programs are read into the central processor registers and are executed by the central processor at scheduled intervals. The results are then returned to central memory.

Information is stored in central memory in the form of words. The length of each word is 60 binary digits (bits). The highly efficient address and data control mechanisms involved permit a word to be moved into or out of central memory in as little as 100 nanoseconds.

An extended core storage unit (ECS) provides additional memory storage and enhances the powerful computing capabilities of the CDC 6000 series computers.

Central processor[edit]

Exchange Jump Package
P A0 B0 = 0
RA (CM) A1 B1
FL (CM) A2 B2
EM A3 B3
RA (ECS) A4 B4
FL (ECS) A5 B5
A6 B6
A7 B7


  • P: Program Address (18 bits)
  • RA: Reference Address
  • FL: Field Length
  • CM: Central Memory (18 bits)
  • ECS: Extended Core Storage (24 bits)
  • EM: Exit Mode (18 bits)
  • A0-A7: Address registers (18 bits)
  • B1-B7: Increment registers (18 bits)
  • X0-X7: Operand registers (60 bits)

The central processor was the high-speed arithmetic unit that functioned as the workhorse of the computer. It performed the addition, subtraction, and logical operations and all of the multiplication, division, incrementing, indexing, and branching instructions for user programs. Note that in the CDC 6000 architecture, the central processing unit performed no input/output (I/O) operations. Input/Output was totally asynchronous, and performed by peripheral processors.

A 6000 series CPU contained 24 operating registers, designated X0-X7, A0-A7, and B0-B7. The eight X registers were each 60 bits long, and used for most data manipulation—both integer and floating point. The eight B registers were 18 bits long, and generally used for indexing and address storage. Register B0 was hard-wired to always return 0. By software convention, register B1 was generally set to 1. (This often allowed the use of 15-bit instructions instead of 30-bit instructions.) The eight 18-bit A registers were 'coupled' to their corresponding X registers in an interesting way: setting an address into any of registers A1 through A5 caused a memory load of the contents of that address into the corresponding X registers. Likewise, setting an address into registers A6 and A7 caused a memory store into that location in memory from X6 or X7. Registers A0 and X0 were not coupled in this way, so could be used as scratch registers. However A0 and X0 were used when addressing CDCs Extended Core Storage (ECS).

Instructions were either 15 or 30 bits long, so there could be up to four instructions per 60-bit word. A 60-bit word could contain any combination of 15-bit and 30-bit instructions that fit within the word, but a 30-bit instruction could not wrap to the next word. The op codes were six bits long. The remainder of the instruction was either three three-bit register fields (two operands and one result), or two registers with an 18-bit immediate constant. All instructions were 'register to register'. For example, the following COMPASS (assembly language) code loads two values from memory, performs a 60-bit integer add, then stores the result:


The central processor used in the CDC 6400 series contained a unified arithmetic element which performed one machine instruction at a time. Depending on instruction type, an instruction could take anywhere from a relatively fast five clock cycles (18-bit integer arithmetic) to as many as 68 clock cycles (60-bit population count). The CDC 6500 was identical to the 6400, but included two identical 6400 CPUs. Thus the CDC 6500 could nearly double the computational throughput of the machine.

The CDC 6600 computer, like the CDC 6400, has just one central processor. However, its central processor offered much greater efficiency. The processor was divided into 10 individual functional units, each of which was designed for a specific type of operation. The function units provided were: branch, Boolean, shift, long integer add, floating-point add, floating-point divide, two floating-point multipliers, and two increment (18-bit integer add) units. Functional unit latencies were between a very fast three clock cycles (increment add) and 29 clock cycles (floating-point divide).

The 6600 processor could issue a new instruction every clock cycle, assuming that various processor (functional unit, register) resources were available. These resources were kept track of by a scoreboard mechanism. Also contributing to keeping the issue rate high was an instruction stack, which cached the contents of several instruction words. Small loops could reside entirely within the stack, eliminating memory latency from instruction fetches.

Both the 6400 and 6600 CPUs had a cycle time of 100 ns (10 MHz). Due to the serial nature of the 6400 CPU, its exact speed was heavily dependent on instruction mix, but generally around 1 MIPS. Floating-point additions were fairly fast at 11 clock cycles, however floating-point multiplication was very slow at 57 clock cycles. Thus its floating point speed would depend heavily on the mix of operations and could be under 200 kFLOPS. The 6600 was, of course, much faster. With good compiler instruction scheduling, the machine could approach its theoretical peak of 10 MIPS. Floating-point additions took four clock cycles, and floating-point multiplies took 10 clocks (but there were two multiply functional units, so two operations could be processing at the same time.) The 6600 could therefore have a peak floating point speed of 2-3 MFLOPS.

The CDC 6700 computer combined the best features of the other three computers. Like the CDC 6500, it had two central processors. One was a CDC 6400/CDC 6500 central processor with the unified arithmetic section; the other was the more efficient CDC 6600 central processor. The combination made the CDC 6700 the fastest and the most powerful of the CDC 6000 series.

Architecture of CDC 6000 series
6000 series
Central Processor
Functional Unit
CDC 6400 12 10 1 24 Unified Arithmetic Section
CDC 6500 12 10 1 24 Unified Arithmetic Section
24 Unified Arithmetic Section
CDC 6600 12 10 1 24 Add, Multiply (2x), Divide, Long add, Shift, Boolean, Increment (2x), Branch
CDC 6700 12 10 1 24 Unified Arithmetic Section
24 Add, Multiply (2x), Divide, Long add, Shift, Boolean, Increment (2x), Branch

Peripheral processors[edit]

The central processor shares access to central memory with ten peripheral processors. Each peripheral processor is an individual computer with its own 1 μs memory of 4K words, each with 12 bits.[16]:p.4-2 (They were somewhat similar to CDC 160A minicomputers, sharing the 12-bit word length and portions of the instruction set.)

Peripheral processors are used primarily for input/output: the transfer of information between central memory and peripheral devices such as disks and magnetic tape units. They relieve the central processor of all input/output tasks, so that it can perform calculations while the peripheral processors are engaged in input/output functions. This feature promotes rapid overall processing of user programs. Nearly all of the operating system ran on the PPs,[29] thus leaving the full power of the Central Processor available for user programs.

Each peripheral processor can add, subtract, and perform logical operations. Special instructions perform data transfer between processor memory and peripheral devices at up to 1 μs per word. The peripheral processors are collectively implemented as a barrel processor. Each executes routines independently of the others. (For comparison, on the IBM 360 series of machines, these processors were called channels.) They are a loose predecessor of bus mastering or Direct memory access.

Instructions used a 6 bit op code, thus leaving only 6 bits for an operand. It was also possible to combine the next word's 12 bits, to form an 18-bit address (the size needed to access the full 131,072 words of Central Memory).[16]:p.4-6

Data channels[edit]

For input or output, each peripheral processor accesses a peripheral device over a communication link called a data channel. One peripheral device can be connected to each data channel; however, a channel can be modified with hardware to service more than one device.

Each peripheral processor can communicate with any peripheral device if another peripheral processor is not using the data channel connected to that device. In other words, only one peripheral processor at a time can use a particular data channel.

Display console[edit]

Console for CDC 6600

In addition to communication between peripheral devices and peripheral processors, communication takes place between the computer operator and the operating system. This was made possible by the computer console, which had two CRT screens.

This display console was a significant departure from conventional computer consoles of the time, which contained hundreds of blinking lights and switches for every state bit in the machine. (See Front panel for an example.) By comparison, the 6000 series console was an elegant design: simple, fast and reliable.

The console screens were calligraphic, not raster based. Analog circuitry actually steered the electron beams to draw the individual characters on the screen. One of the peripheral processors ran a dedicated program called "DSD" (Dynamic System Display), which drove the console. Coding in DSD needed to be fast as it needed to continually redraw the screen quickly enough to avoid visible flicker.

DSD displayed information about the system and the jobs in process. The console also included a keyboard through which the operator could enter requests to modify stored programs and display information about jobs in or awaiting execution.

A full-screen editor, called O26 (after the IBM model 026 key punch, with the first character made alphabetic due to operating system restrictions), could be run on the operator console. This text editor appeared in 1967—which made is one of the first full-screen editors. (Unfortunately, it took CDC another 15 years to offer FSE, a full-screen editor for normal time-sharing users on CDCs Network Operating System.)

There were also a variety of games that were written using the operator console. These included BAT (a baseball game), KAL (a kaleidoscope), DOG (Snoopy flying his doghouse across the screens), ADC (Andy Capp strutting across the screens), EYE (changed the screens into giant eyeballs, then winked them), PAC (a Pac-Man-like game), a lunar lander simulator, and more.

Minimum configuration[edit]

The minimum hardware requirements of a CDC 6000 series computer system consisted of the computer, including 32,768 words of central memory storage, any combination of disks, disk packs, or drums to provide 24 million characters of mass storage, a punched card reader, punched card punch, printer with controllers, and two 7-track magnetic tape units.

Larger systems could be obtained by including optional equipment such as additional central memory,[30][16] extended core storage (ECS), additional card readers, punches, printers, and tape units. Graphic plotters and microfilm recorders were also available.


  • CDC 405 Card Reader - Unit reads 80-column cards at 1200 cards a minute and 51-column cards at 1600 cards per minute. Each tray holds 4000 cards to reduce the rate of required service. [31]
  • CDC 6602/6612 Console Display
  • CDC 6603 Disk System
  • CDC 626 Magnetic Tape Transports
  • CDC 6682/6683 Satellite Coupler
  • CDC 6681 Data Channel Converter[10]


The CDC 6600 was the flagship. The CDC 6400 was a slower, lower-performance CPU that cost significantly less.

The CDC 6500 was a dual CPU 6400. The CDC 6700 was also a dual CPU machine, but had one 6600 CPU and one 6400 CPU. The CDC 6415 was an even cheaper and slower machine; it had a 6400 CPU but with only seven PPUs instead of the normal ten.

The 6600[edit]

The CDC 6600 was the flagship mainframe supercomputer of the 6000 series of computer systems manufactured by Control Data Corporation. Generally considered to be the first successful supercomputer, it outperformed its fastest predecessor, the IBM 7030 Stretch, by a factor of three. With performance of up to three megaFLOPS,[32][33] the CDC 6600, of which about 100 were sold,[34] was the world's fastest computer from 1964 to 1969, when it relinquished that status to its successor, the CDC 7600.[35][27]

The CDC 6600 anticipated the RISC design philosophy and, unusually, employed a ones'-complement representation of integers. Its successors would continue the architectural tradition for more than 30 years until the late 1980s, and were the last chips designed with ones'-complement integers.[36]

The first CDC 6600's were delivered in 1965 to the Livermore and Los Alamos National Labs (managed by the University of California). Serial #4 went to the Courant Institute of Mathematical Sciences Courant Institute at NYU in Greenwich Village, New York CIty. The first delivery outside the US went to CERN laboratory near Geneva, Switzerland,[37] where it was used to analyse the two to three million photographs of bubble-chamber tracks that CERN experiments were producing every year. In 1966 another CDC 6600 was delivered to the Lawrence Radiation Laboratory, part of the University of California at Berkeley, where it was used for the analysis of nuclear events photographed inside the Alvarez bubble chamber.[38] The University of Texas at Austin had one delivered for its Computer Science and Mathematics Departments, and installed underground on its main campus, tucked into a hillside with one side exposed, for cooling efficiency.

A CDC 6600 is on display at the Computer History Museum in Mountain View, California.

The 6400[edit]

The CDC 6400, a member of the CDC 6000 series, was a mainframe computer made by Control Data Corporation in the 1960s. The central processing unit was architecturally compatible with the CDC 6600. In contrast to the 6600, which had 10 parallel functional units which could work on multiple instructions at the same time, the 6400 had a unified arithmetic unit, which could only work on a single instruction at a time. This resulted in a slower, lower-performance CPU, but one that cost significantly less. Memory, peripheral processor-based input/output (I/O), and peripherals were otherwise identical to the 6600.

In 1966, the Computing Center (German: RechenZentrum) of the RWTH Aachen University acquired a CDC 6400, the first Control Data supercomputer in Germany and the second one in Europe after the European Organization for Nuclear Research (CERN). It served the entire university also by 64 remote-line teletypes (TTY) until it was replaced by a CDC Cyber 175 computer in 1976.[39]

Dual CPU systems[edit]

The 6500[edit]

CDC 6500
CDC 6500.jpg
Open panels of the CDC 6500 undergoing restoration at Living Computers: Museum + Labs in Seattle.
Developer Seymour Cray
Manufacturer Control Data Corporation
Product family CDC 6000 series
Type Supercomputer
Release date 1967 (1967)
Introductory price $8 million ~ equivalent to $63,124,464 in 2017
Operating system SCOPE
CPU Dual 6400, up to 40MHz
Memory 65,000 60-bit words
Display DD60
Weight 10,000+ Lbs.
Predecessor IBM 7030 Stretch
Successor CDC 7600

The CDC 6500, which features a dual CPU 6400,[40] is the third supercomputer in the 6000 series manufactured by the Control Data Corporation and designed by supercomputer pioneer Seymour Cray.[24] The first 6500 was announced in 1964 and was delivered in 1967.[41]

It includes twelve different independent computers. Ten are peripheral and control processors, each of which have a separate memory and can run programs separately from each other and the two 6400 central processors.[10] Instead of being air-cooled, it has a liquid refrigeration system and each of the three bays of the computer has its own cooling unit.[42]

CDC 6500 systems were installed at:

The 6700[edit]

Composed of a 6600 and a 6400, the CDC 6700 was the most powerful of the 6000 series.

See also[edit]

  • CDC Cyber - contained the successors to the 6000 series computers


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  2. ^ "Controversy over export license". Computerworld. September 12, 1977. p. 94. 
  3. ^ "Remember when - Southern Maryland". 
  4. ^ Lath Carlson. "CDC 6500 supercomputer at the Living Computers Museum". 
  5. ^ "Partitioned-Data-Set Utility Routines for the Control Data CDC-6700". 
  6. ^ "Control Data Corporation, CDC-6600 & 7600". 
  7. ^ "CDC 6000s at Michigan State University". 
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  14. ^ Paul B. Schneck (2012). Supercomputer Architecture. p. 47. ISBN 1461579570. 
  15. ^ In later years, special editions of the 6000 series were delivered to some customers with more or fewer, somewhat like IBM's RPQs.
  16. ^ a b c d e f g Control Data 6000 Series Hardware Reference Manual (PDF). 1978. 
  17. ^ The other-than-10 PPU configuration was non-standard, and problems were documented.
  18. ^ "IT History Society". 
  19. ^ a configuration similar to IBM's Attached Support Processor, which used a high end Main processor and a high end Support Processor. A 1967-introduced combination was a 360/91 and a 360/75.
  20. ^ "COMPASS for 24 bit machines" (PDF). 
  21. ^ "COMPASS for 48 bit machines" (PDF). 
  22. ^ "CDC delivered an early version of their SCOPE operating system for the 3600" Henley, Ernest J.; Lewins, Jeffery (2014). Advances in Nuclear Science and Technology. ISBN 1483215660. 
  23. ^ Living Computers: Museum + Labs]
  24. ^ a b "CDC 6500". Living Computer Museum. Retrieved 25 July 2016. 
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  26. ^ "In 1964 Cray's CDC 6600 replaced Stretch as the fastest computer on earth." Andreas Sofroniou (2013). EXPERT SYSTEMS, KNOWLEDGE ENGINEERING FOR HUMAN REPLICATION. ISBN 1291595090. 
  27. ^ a b |url= |title=CDC 7600}}
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  29. ^ "The Illinois Zephyr". 
  30. ^ The official list of supported Central Memory configurations is: 16,384 / 32,768 / 49,152 / 65,536 / 98,304 or 131,072.
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  34. ^ "CDC 6600's Five Year Reign". 
  35. ^ "The 7600 design lasted longer than any other supercomputer design. It had the highest performance of any computer from its introduction in 1969 till the introduction of the Cray 1 in 1976.">
  36. ^ The UNIVAC 1100/2200 series still provides a ones'-complement environment, but using two's complement hardware.
  37. ^ "The CDC 6600 arrives at CERN". CERN Timelines. 
  38. ^ "Bumper Crop". Research Review. Lawrence Berkeley Laboratory. 1981. 
  39. ^ "Chronik des heutigen Rechen- und Kommunikationszentrums (RZ) der RWTH Aachen" (in German). ReZe RWTH Aachen. Retrieved 2013-12-13. 
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  45. ^ Enterprise, I. D. G. (5 June 1978). "Computerworld". 12 (23). IDG Enterprise. Retrieved 25 July 2016. 


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