IBM z13
| History of IBM mainframes, 1952–present |
|---|
| Market name |
| Architecture |
| General information | |
|---|---|
| Launched | 2015 |
| Designed by | IBM |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 5 GHz |
| Cache | |
| L1 cache | 96 I-L1 128 D-L1 per core |
| L2 cache | 2 MB I-L2 2 MB D-L2 per core |
| L3 cache | 64 MB shared |
| Architecture and classification | |
| Instruction set | z/Architecture |
| Physical specifications | |
| Cores |
|
| History | |
| Predecessor | zEC12 |
The z13 microprocessor is a chip made by IBM for their z13 mainframe computers, announced on January 14, 2015.[2] Manufactured at GlobalFoundries East Fishkill, New York fabrication plant (formerly IBM's own plant).[1] IBM stated that it is the world's fastest microprocessor and is about 10% faster than its predecessor the zEC12 in general single-threaded computing,[3] but significantly more when doing specialized tasks.[4]
Description
The Processor Unit chip (PU chip) measures 678 mm2 and consists of 3.99 billion transistors fabricated using IBM's 22 nm CMOS silicon on insulator fabrication process, using 17 metal layers and supporting speeds of 5.2 GHz, which is less than its predecessor, the zEC12.[3][5] The PU chip can have six, seven or eight cores (or "processor units" in IBM's parlance) enabled depending on configuration. New for the z13 is that the PU chip comes packaged in single chip modules, which is a big change from all previous mainframe processors that were mounted on large multi-chip modules. A computer drawer consists of six PU chips and two Storage Controller (SC) chips.[3]
The cores implement the CISC z/Architecture with a superscalar, out-of-order pipeline and instructions. It has facilities related to transactional memory, and new features such as two-way simultaneous multithreading (SMT),139 new SIMD instructions, data compression, improved cryptography and logical partitioning. The cores have numerous other enhancements such as a new superscalar pipeline, on-chip cache design and error correction.[3]
The instruction pipeline has an instruction queue that can fetch 6 instructions per cycle; and issue up to 10 instructions per cycle. Each core has a private 96 KB L1 instruction cache, a private 128 KB L1 data cache, a private 2 MB L2 cache instruction cache, and a private 2 MB L2 data cache. In addition, there is a 64 MB shared L3 cache implemented in eDRAM. There's also an additional shared L1 cache used for compression and cryptography operations.[3]
The z13 chip has on board multi-channel DDR3 RAM memory controller supporting a RAID-like configuration to recover from memory faults. The z13 also includes two GX bus as well as two new Gen 3 PCIe controllers for accessing host channel adapters and peripherals.[3]
Storage Controller
A compute drawer consists of two sets of three PU chips and one Storage Controller chip (SC chip). Even though each PU chip has 64 MB L3 cache shared by the 8 cores and other on-die facilities the SC chip adds 480 MB off-die L4 cache shared by three PU chips. The two SC chips adds a total of 960 MB L4 cache per drawer. The SC chips also handle the communications between the sets of three PU chips and to other drawers. The SC chip is manufactured on the same 22 nm process as the z13 PU chips, has 15 metal layers, measures 28.4 × 23.9 mm (678 mm2), consists of 7.1 billion transistors and runs at half the clock frequency of the CP chip.[3][5]
See also
References
- ^ a b IBM Systems Get Breathing Room With Globalfoundries Chip Deal
- ^ IBM Launches z13 Mainframe -- Most Powerful and Secure System Ever Built
- ^ a b c d e f g IBM z13 Technical Introduction
- ^ IBM Renews Mainframe With z13
- ^ a b J. Warnock et al., 22nm Next-Generation IBM System z Microprocessor. 2015 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).