The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which silicon integrated circuit chips are built. The process utilizes the surface passivation and thermal oxidation methods.
The planar process was developed at Fairchild Semiconductor in 1959 by Jean Hoerni, who adopted the surface passivation and thermal oxidation methods originally developed by Mohamed Atalla at Bell Labs in 1957. Hoerni's planar process was in turn the basis for Robert Noyce's invention of the monolithic integrated circuit chip at Fairchild, later in 1959.
The key concept is to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allows the use of a series of exposures on a substrate (silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization, and the concepts of p–n junction isolation and surface passivation, it is possible to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.
The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.
In 1955, Carl Frosch and Lincoln Derick at Bell Telephone Laboratories (BTL) accidentally discovered that silicon dioxide could be grown on silicon. Later in 1958, they proposed that silicon oxide layers could protect silicon surfaces during diffusion processes, and could be used for diffusion masking.
Surface passivation, the process by which a semiconductor surface is rendered inert, and does not change semiconductor properties as a result of interaction with air or other materials in contact with the surface or edge of the crystal, was first developed by Egyptian engineer Mohamed M. Atalla at BTL in the late 1950s. He discovered that the formation of a thermally grown silicon dioxide (SiO2) layer greatly reduced the concentration of electronic states at the silicon surface, and discovered the important quality of SiO2 films to preserve the electrical characteristics of p–n junctions and prevent these electrical characteristics from deteriorating by the gaseous ambient environment. He found that silicon oxide layers could be used to electrically stabilize silicon surfaces. He developed the surface passivation process, a new method of semiconductor device fabrication that involves coating a silicon wafer with an insulating layer of silicon oxide so that electricity could reliably penetrate to the conducting silicon below. By growing a layer of silicon dioxide on top of a silicon wafer, Atalla was able to overcome the surface states that prevented electricity from reaching the semiconducting layer.
Atalla first published his findings in 1957. According to Fairchild Semiconductor engineer Chih-Tang Sah, the surface passivation process developed by Atalla and his team was "the most important and significant technology advance, which blazed the trail" that led to the silicon integrated circuit.
At a 1958 Electrochemical Society meeting, Mohamed Atalla presented a paper about the surface passivation of PN junctions by thermal oxidation, based on his 1957 BTL memos, and demonstrated silicon dioxide's passivating effect on a silicon surface. This was the first demonstration to show that high-quality silicon dioxide insulator films could be grown thermally on the silicon surface to protect the underlying silicon p-n junction diodes and transistors.
Swiss engineer Jean Hoerni attended the same 1958 meeting, and was intrigued by Atalla's presentation. Hoerni came up with the "planar idea" one morning while thinking about Atalla's device. Taking advantage of silicon dioxide's passivating effect on the silicon surface, Hoerni proposed to make transistors that were protected by a layer of silicon dioxide. This led to the first successful product implementation of the Atalla silicon transistor passivation technique by thermal oxide.
Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.
In 1959, Robert Noyce built on Hoerni's work with his conception of an integrated circuit (IC), which added a layer of metal to the top of Hoerni's basic structure to connect different components, such as transistors, capacitors, or resistors, located on the same piece of silicon. The planar process provided a powerful way of implementing an integrated circuit that was superior to earlier conceptions of the integrated circuit. Noyce's invention was the first monolithic IC chip.
Early versions of the planar process used a photolithography process using near-ultraviolet light from a mercury vapor lamp. As of 2011, small features are typically made with 193 nm "deep" UV lithography. Some researchers use even higher-energy extreme ultraviolet lithography.
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